Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25026

1

T1

20

T4

10

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21727

1

T1

20

T4

10

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3299

1

T7

4

T14

1

T18

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19446

1

T1

20

T4

10

T5

20

auto[1]

5580

1

T7

4

T12

5

T13

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T4

10

T5

20

auto[1]

3822

1

T7

2

T9

2

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T264	1		-	-		-	-
values[0]	69	1			T12	1		T210	5		T169	4
values[1]	538	1			T12	5		T17	14		T81	27
values[2]	751	1			T52	25		T53	13		T171	1
values[3]	736	1			T14	1		T16	4		T137	12
values[4]	759	1			T81	11		T144	5		T63	1
values[5]	2821	1			T7	4		T15	26		T19	1
values[6]	495	1			T70	33		T171	15		T173	12
values[7]	690	1			T151	1		T138	28		T139	1
values[8]	755	1			T13	5		T144	12		T139	40
values[9]	1180	1			T9	5		T18	2		T50	2
minimum	16231	1			T1	20		T4	10		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	812	1			T12	6		T17	14		T52	25
values[1]	747	1			T14	1		T171	1		T142	1
values[2]	735	1			T16	4		T137	12		T70	10
values[3]	2933	1			T7	4		T15	26		T19	1
values[4]	536	1			T50	28		T61	4		T151	2
values[5]	642	1			T70	33		T151	1		T139	1
values[6]	699	1			T13	5		T138	28		T139	8
values[7]	687	1			T144	12		T139	32		T146	12
values[8]	843	1			T9	5		T18	2		T50	2
values[9]	159	1			T160	1		T71	27		T188	1
minimum	16233	1			T1	20		T4	10		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

4077

1

T7

1

T9

1

T12

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	5		T17	1		T52	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T53	1		T81	13		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T171	1		T165	13		T211	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T14	1		T142	1		T239	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T16	3		T70	6		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T137	12		T138	5		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1655	1			T15	3		T19	1		T51	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	3		T43	1		T199	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T151	1		T81	3		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T50	16		T61	3		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T151	1		T173	12		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T70	20		T139	1		T265	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	4		T188	1		T166	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T138	12		T139	8		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T144	10		T146	12		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T139	16		T171	1		T147	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	3		T137	2		T147	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T18	1		T50	1		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T160	1		T71	14		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T234	7		T153	17		T266	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T103	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	1		T17	13		T52	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T53	12		T81	14		T163	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T165	3		T223	10		T233	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T75	6		T152	15		T255	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T16	1		T70	4		T145	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T138	6		T229	10		T260	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T15	23		T97	3		T70	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T7	1		T199	12		T187	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T81	8		T171	14		T224	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T50	12		T61	1		T267	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T169	5		T153	1		T218	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T70	13		T265	13		T47	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T13	1		T166	16		T207	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T138	16		T187	1		T156	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T144	2		T231	11		T170	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T139	16		T171	5		T147	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	2		T147	10		T47	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T18	1		T50	1		T208	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T71	13		T209	8		T215	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T153	15		T256	1		T268	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T103	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T264	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T12	1		T256	13		T269	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T210	5		T169	1		T270	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	4		T17	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T81	13		T163	1		T168	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T52	13		T171	1		T148	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T53	1		T39	5		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T16	3		T70	6		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	1		T137	12		T138	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T81	3		T144	3		T63	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T164	13		T199	13		T187	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T15	3		T19	1		T51	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	3		T50	16		T61	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T171	1		T173	12		T188	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T70	20		T169	1		T170	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T151	1		T249	1		T207	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T138	12		T139	1		T168	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	4		T144	10		T166	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T139	24		T171	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T9	3		T137	2		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T18	1		T50	1		T208	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T256	15		T269	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T169	3		T270	15		T183	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T12	1		T17	13		T145	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T81	14		T163	12		T209	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T52	12		T148	16		T165	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T53	12		T39	2		T41	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T16	1		T70	4		T145	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T138	6		T229	10		T260	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T81	8		T144	2		T140	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T199	12		T187	3		T252	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T15	23		T97	3		T70	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T7	1		T50	12		T61	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T171	14		T153	1		T218	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T70	13		T170	4		T214	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T207	8		T226	9		T212	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T138	16		T265	13		T47	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	1		T144	2		T166	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T139	16		T171	5		T147	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T9	2		T147	10		T71	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T18	1		T50	1		T208	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	4		T17	14		T52	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T53	13		T81	15		T163	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T171	1		T165	4		T211	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T14	1		T142	1		T239	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T16	3		T70	5		T145	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T137	1		T138	7		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T15	26		T19	1		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	3		T43	1		T199	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T151	1		T81	9		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T50	13		T61	3		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T151	1		T173	1		T169	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T70	14		T139	1		T265	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	4		T188	1		T166	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T138	17		T139	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T144	3		T146	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T139	17		T171	6		T147	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T9	4		T137	1		T147	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T18	2		T50	2		T208	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T160	1		T71	14		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T234	1		T153	16		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T103	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	2		T52	12		T165	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T81	12		T168	12		T39	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T165	12		T211	10		T223	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T239	10		T75	4		T152	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T70	5		T62	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T137	11		T138	4		T164	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T51	14		T64	18		T70	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T7	1		T199	12		T223	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T81	2		T146	9		T234	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T50	15		T61	1		T173	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T173	11		T218	1		T261	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T70	19		T170	1		T230	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	1		T166	14		T207	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T138	11		T139	7		T168	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T144	9		T146	11		T231	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T139	15		T147	5		T210	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	1		T137	1		T147	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T216	9		T152	16		T157	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T71	13		T215	4		T271	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T234	6		T153	16		T266	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T264	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T12	1		T256	16		T269	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T210	1		T169	4		T270	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	3		T17	14		T145	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T81	15		T163	13		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T52	13		T171	1		T148	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T53	13		T39	3		T41	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T16	3		T70	5		T145	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	1		T137	1		T138	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T81	9		T144	3		T63	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T164	1		T199	13		T187	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T15	26		T19	1		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	3		T50	13		T61	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T171	15		T173	1		T188	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T70	14		T169	1		T170	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T151	1		T249	1		T207	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T138	17		T139	1		T168	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	4		T144	3		T166	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T139	18		T171	6		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T9	4		T137	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T18	2		T50	2		T208	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T256	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T210	4		T189	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T12	2		T165	2		T206	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T81	12		T168	12		T152	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T52	12		T148	13		T165	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T39	4		T75	4		T255	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T16	1		T70	5		T62	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T137	11		T138	4		T38	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T81	2		T144	2		T168	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T164	12		T199	12		T187	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T51	14		T64	18		T70	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	1		T50	15		T61	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T173	11		T218	1		T261	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T70	19		T170	1		T230	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T207	7		T261	3		T245	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T138	11		T168	8		T156	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	1		T144	9		T166	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T139	22		T147	5		T38	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T9	1		T137	1		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T216	9		T234	6		T152	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

auto[0]

4077

1

T7

1

T9

1

T12

2