Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25026

1

T1

20

T4

10

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21779

1

T1

20

T4

10

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3247

1

T7

4

T9

5

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19382

1

T1

20

T4

10

T5

20

auto[1]

5644

1

T7

4

T9

5

T13

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T4

10

T5

20

auto[1]

3822

1

T7

2

T9

2

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	316	1			T173	12		T210	11		T249	3
values[0]	1	1			T174	1		-	-		-	-
values[1]	674	1			T208	14		T63	1		T147	22
values[2]	688	1			T70	33		T139	8		T146	1
values[3]	596	1			T12	1		T13	5		T14	1
values[4]	636	1			T18	2		T137	2		T151	1
values[5]	645	1			T151	1		T160	1		T145	10
values[6]	673	1			T9	5		T70	14		T160	1
values[7]	689	1			T7	4		T12	5		T50	28
values[8]	2922	1			T15	26		T17	14		T19	1
values[9]	955	1			T70	10		T151	1		T144	12
minimum	16231	1			T1	20		T4	10		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	719	1			T70	33		T63	1		T147	22
values[1]	616	1			T12	1		T139	8		T146	1
values[2]	601	1			T13	5		T14	1		T16	4
values[3]	651	1			T18	2		T137	2		T151	1
values[4]	724	1			T151	1		T160	1		T144	5
values[5]	632	1			T70	14		T160	1		T171	6
values[6]	2978	1			T7	4		T9	5		T12	5
values[7]	711	1			T17	14		T50	2		T53	13
values[8]	972	1			T70	10		T151	1		T144	12
values[9]	71	1			T249	3		T152	29		T246	1
minimum	16351	1			T1	20		T4	10		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

4077

1

T7

1

T9

1

T12

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T70	20		T63	1		T168	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T147	12		T169	1		T170	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T146	1		T140	1		T168	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	1		T139	8		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	1		T16	3		T81	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	4		T145	1		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T145	1		T138	5		T39	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T18	1		T137	2		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T151	1		T173	1		T148	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T160	1		T144	3		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T70	8		T160	1		T38	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T171	1		T250	2		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1672	1			T12	4		T15	3		T19	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	3		T9	3		T50	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T17	1		T50	1		T61	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T53	1		T216	10		T26	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T151	1		T144	10		T252	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T70	6		T138	12		T146	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T249	3		T256	1		T272	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T152	17		T246	1		T257	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16156	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T208	1		T174	1		T263	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T70	13		T229	10		T47	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T147	10		T170	4		T187	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T140	6		T209	13		T225	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T75	6		T187	3		T152	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T16	1		T81	8		T145	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T13	1		T145	3		T147	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T145	9		T138	6		T39	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T18	1		T165	3		T265	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T148	16		T230	6		T111	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T144	2		T142	6		T166	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T70	6		T41	6		T71	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T171	5		T214	14		T255	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T12	1		T15	23		T52	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T7	1		T9	2		T50	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T17	13		T50	1		T61	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T53	12		T216	8		T26	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T144	2		T252	7		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T70	4		T138	16		T199	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T256	1		T272	13		T273	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T152	12		T257	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T7	1		T12	3		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T208	13		T274	11		T268	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T249	3		T213	4		T256	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T173	12		T210	11		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T174	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T63	1		T168	8		T229	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T208	1		T147	12		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T70	20		T146	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T139	8		T141	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	1		T16	3		T81	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	1		T13	4		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T62	5		T138	5		T39	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T18	1		T137	2		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T151	1		T145	1		T148	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T160	1		T141	1		T168	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T70	8		T160	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	3		T144	3		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	4		T52	13		T81	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	3		T50	16		T137	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1655	1			T15	3		T17	1		T19	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T53	1		T141	1		T216	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T151	1		T144	10		T252	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T70	6		T138	12		T146	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T256	1		T217	1		T212	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T104	22		T247	9		T257	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T229	10		T47	6		T207	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T208	13		T147	10		T170	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T70	13		T140	6		T209	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T152	15		T245	9		T258	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	1		T81	8		T145	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T13	1		T165	3		T75	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T62	2		T138	6		T39	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	1		T145	3		T147	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T145	9		T148	16		T28	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T142	6		T166	16		T47	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T70	6		T71	13		T231	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T9	2		T144	2		T171	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	1		T52	12		T81	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	1		T50	12		T214	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T15	23		T17	13		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T53	12		T216	8		T26	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T144	2		T252	7		T260	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T70	4		T138	16		T199	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T70	14		T63	1		T168	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T147	11		T169	1		T170	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T146	1		T140	7		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	1		T139	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T14	1		T16	3		T81	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T13	4		T145	4		T171	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T145	10		T138	7		T39	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T18	2		T137	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T151	1		T173	1		T148	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T160	1		T144	3		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T70	7		T160	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T171	6		T250	2		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T12	3		T15	26		T19	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	3		T9	4		T50	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T17	14		T50	2		T61	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T53	13		T216	9		T26	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T151	1		T144	3		T252	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T70	5		T138	17		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T249	1		T256	2		T272	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T152	13		T246	1		T257	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16249	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T208	14		T174	1		T263	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T70	19		T168	7		T229	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T147	11		T170	1		T152	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T168	8		T210	18		T223	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T139	7		T75	4		T187	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T16	1		T81	2		T62	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	1		T147	5		T275	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T138	4		T39	4		T206	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T137	1		T165	12		T206	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T148	13		T38	12		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T144	2		T168	12		T166	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T70	7		T38	13		T71	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T255	12		T261	10		T262	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T12	2		T51	14		T52	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	1		T9	1		T50	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T61	1		T173	11		T223	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T216	9		T26	1		T223	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T144	9		T252	15		T263	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T70	5		T138	11		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T249	2		T276	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T152	16		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T277	7		T278	3		T279	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T263	6		T274	11		T280	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T249	1		T213	1		T256	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T173	1		T210	1		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T174	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T63	1		T168	1		T229	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T208	14		T147	11		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T70	14		T146	1		T140	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T139	1		T141	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	1		T16	3		T81	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	1		T13	4		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T62	5		T138	7		T39	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T18	2		T137	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T151	1		T145	10		T148	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T160	1		T141	1		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T70	7		T160	1		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	4		T144	3		T171	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	3		T52	13		T81	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	3		T50	13		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T15	26		T17	14		T19	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T53	13		T141	1		T216	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T151	1		T144	3		T252	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T70	5		T138	17		T146	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T249	2		T213	3		T277	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T173	11		T210	10		T104	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T168	7		T229	8		T207	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T147	11		T170	1		T152	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T70	19		T168	8		T210	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T139	7		T152	10		T245	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T16	1		T81	2		T139	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	1		T165	12		T75	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T62	2		T138	4		T39	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T137	1		T147	5		T206	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T148	13		T38	12		T206	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T168	12		T166	14		T210	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T70	7		T38	13		T71	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T9	1		T144	2		T252	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	2		T52	12		T81	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T7	1		T50	15		T137	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T51	14		T64	18		T61	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T216	9		T26	1		T223	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T144	9		T252	15		T260	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T70	5		T138	11		T146	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

auto[0]

4077

1

T7

1

T9

1

T12

2