Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25026

1

T1

20

T4

10

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19363

1

T1

20

T4

10

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

5663

1

T9

5

T12

1

T13

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19226

1

T1

20

T4

10

T5

20

auto[1]

5800

1

T12

6

T13

5

T15

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T4

10

T5

20

auto[1]

3822

1

T7

2

T9

2

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	35	1			T289	1		T290	34		-	-
values[0]	74	1			T231	25		T170	2		T218	4
values[1]	497	1			T141	2		T26	4		T165	16
values[2]	528	1			T16	4		T17	14		T50	2
values[3]	645	1			T137	14		T144	5		T139	32
values[4]	688	1			T9	5		T12	1		T18	2
values[5]	618	1			T7	4		T13	5		T70	43
values[6]	658	1			T81	27		T160	1		T145	4
values[7]	541	1			T12	5		T61	4		T70	14
values[8]	821	1			T146	12		T163	13		T173	12
values[9]	3690	1			T14	1		T15	26		T19	1
minimum	16231	1			T1	20		T4	10		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	651	1			T141	3		T26	4		T165	16
values[1]	2881	1			T15	26		T16	4		T17	14
values[2]	764	1			T9	5		T18	2		T137	2
values[3]	503	1			T7	4		T12	1		T52	25
values[4]	665	1			T13	5		T70	43		T81	27
values[5]	633	1			T12	5		T160	1		T145	4
values[6]	598	1			T70	14		T208	14		T145	10
values[7]	864	1			T50	28		T61	4		T146	12
values[8]	987	1			T14	1		T19	1		T151	1
values[9]	223	1			T53	13		T81	11		T144	12
minimum	16257	1			T1	20		T4	10		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

4077

1

T7

1

T9

1

T12

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T141	1		T206	8		T211	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T141	2		T26	3		T165	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T17	1		T50	1		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1623	1			T15	3		T16	3		T51	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T18	1		T151	2		T144	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	3		T137	2		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	3		T52	13		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	1		T164	13		T249	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T70	6		T138	5		T165	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T13	4		T70	20		T81	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	4		T160	1		T147	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T145	1		T216	10		T173	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T208	1		T62	5		T146	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T70	8		T145	1		T139	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T61	3		T146	12		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T50	16		T239	11		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T19	1		T151	1		T138	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T14	1		T139	1		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T81	3		T144	10		T165	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T53	1		T71	14		T211	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T228	18		T170	1		T291	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T209	8		T231	9		T230	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T26	1		T165	3		T169	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T17	13		T50	1		T147	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	956	1			T15	23		T16	1		T97	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T18	1		T144	2		T199	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	2		T142	6		T193	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	1		T52	12		T225	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T187	1		T215	3		T262	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T70	4		T138	6		T255	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	1		T70	13		T81	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	1		T147	2		T223	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T145	3		T216	8		T281	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T208	13		T62	2		T140	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T70	6		T145	9		T223	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T61	1		T41	6		T166	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T50	12		T169	3		T187	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T138	16		T148	16		T75	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T163	12		T207	13		T267	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T81	8		T144	2		T165	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T53	12		T71	13		T214	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T170	1		T291	5		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T289	1		T290	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T230	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T231	14		T170	1		T218	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T141	1		T206	8		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T141	1		T26	3		T165	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T17	1		T50	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	3		T141	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T144	3		T173	1		T168	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T137	14		T139	16		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T18	1		T52	13		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	3		T12	1		T164	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	3		T70	6		T138	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	4		T70	20		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T160	1		T147	6		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T81	13		T145	1		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	4		T61	3		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T70	8		T145	1		T139	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T146	12		T173	12		T166	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T163	1		T206	13		T239	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T19	1		T151	1		T81	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1879	1			T14	1		T15	3		T50	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T290	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T230	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T231	11		T170	1		T218	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T209	8		T231	9		T104	32
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T26	1		T165	3		T169	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T17	13		T50	1		T147	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T16	1		T233	4		T155	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T144	2		T199	12		T265	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T139	16		T171	14		T142	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T18	1		T52	12		T225	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	2		T232	14		T245	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	1		T70	4		T138	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T13	1		T70	13		T145	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T147	2		T252	10		T152	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T81	14		T145	3		T171	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	1		T61	1		T208	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T70	6		T145	9		T260	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T166	16		T152	12		T224	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T163	12		T223	2		T169	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T81	8		T144	2		T138	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1236	1			T15	23		T50	12		T53	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T141	1		T206	1		T211	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T141	2		T26	3		T165	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T17	14		T50	2		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1303	1			T15	26		T16	3		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T18	2		T151	2		T144	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	4		T137	1		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	3		T52	13		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	1		T164	1		T249	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T70	5		T138	7		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	4		T70	14		T81	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	3		T160	1		T147	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T145	4		T216	9		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T208	14		T62	5		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T70	7		T145	10		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T61	3		T146	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T50	13		T239	1		T169	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T19	1		T151	1		T138	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T14	1		T139	1		T163	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T81	9		T144	3		T165	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T53	13		T71	14		T211	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T228	1		T170	2		T291	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T206	7		T211	10		T231	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T26	1		T165	12		T231	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T147	11		T243	9		T283	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1276	1			T16	1		T51	14		T64	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T144	2		T168	15		T199	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	1		T137	1		T261	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T7	1		T52	12		T292	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T164	12		T249	2		T215	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T70	5		T138	4		T165	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	1		T70	19		T81	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	2		T147	5		T38	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T216	9		T173	11		T210	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T62	2		T146	9		T173	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T70	7		T139	7		T206	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T61	1		T146	11		T166	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T50	15		T239	10		T28	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T138	11		T148	13		T38	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T207	11		T267	1		T152	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T81	2		T144	9		T165	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T71	13		T211	7		T282	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T228	17		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T289	1		T290	18		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T230	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T231	12		T170	2		T218	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T141	1		T206	1		T209	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T141	1		T26	3		T165	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T17	14		T50	2		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T16	3		T141	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T144	3		T173	1		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T137	2		T139	17		T171	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T18	2		T52	13		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	4		T12	1		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	3		T70	5		T138	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T13	4		T70	14		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T160	1		T147	3		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T81	15		T145	4		T171	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	3		T61	3		T208	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T70	7		T145	10		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T146	1		T173	1		T166	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T163	13		T206	1		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T19	1		T151	1		T81	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1627	1			T14	1		T15	26		T50	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T290	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T230	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T231	13		T218	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T206	7		T231	8		T104	30
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T26	1		T165	12		T228	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T147	11		T211	10		T215	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T16	1		T233	3		T234	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T144	2		T168	8		T199	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T137	12		T139	15		T237	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T52	12		T168	7		T275	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	1		T164	12		T249	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	1		T70	5		T138	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	1		T70	19		T223	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T147	5		T38	1		T165	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T81	12		T216	9		T173	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	2		T61	1		T62	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T70	7		T139	7		T206	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T146	11		T173	11		T166	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T206	12		T239	10		T223	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T81	2		T144	9		T138	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1488	1			T50	15		T51	14		T64	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

auto[0]

4077

1

T7

1

T9

1

T12

2