Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25026

1

T1

20

T4

10

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21724

1

T1

20

T4

10

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3302

1

T9

5

T13

5

T16

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18783

1

T1

20

T4

10

T5

20

auto[1]

6243

1

T9

5

T12

5

T14

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T4

10

T5

20

auto[1]

3822

1

T7

2

T9

2

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	36	1			T242	7		T293	6		T294	10
values[0]	123	1			T295	1		T291	6		T281	15
values[1]	827	1			T16	4		T17	14		T53	13
values[2]	2828	1			T12	1		T15	26		T51	15
values[3]	575	1			T70	33		T208	14		T151	1
values[4]	707	1			T50	28		T139	32		T216	18
values[5]	632	1			T7	4		T9	5		T12	5
values[6]	725	1			T52	25		T138	11		T164	13
values[7]	684	1			T18	2		T137	12		T81	11
values[8]	618	1			T160	1		T171	1		T140	7
values[9]	1040	1			T19	1		T61	4		T137	2
minimum	16231	1			T1	20		T4	10		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1034	1			T12	1		T16	4		T17	14
values[1]	2868	1			T15	26		T51	15		T64	19
values[2]	521	1			T208	14		T81	27		T63	1
values[3]	858	1			T9	5		T12	5		T50	28
values[4]	540	1			T7	4		T13	5		T14	1
values[5]	798	1			T18	2		T52	25		T81	11
values[6]	645	1			T137	12		T160	1		T171	1
values[7]	670	1			T19	1		T140	7		T141	1
values[8]	682	1			T61	4		T137	2		T151	1
values[9]	178	1			T171	6		T210	11		T223	23
minimum	16232	1			T1	20		T4	10		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

4077

1

T7

1

T9

1

T12

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T12	1		T70	6		T146	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T16	3		T17	1		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1546	1			T15	3		T51	15		T64	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T70	20		T151	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T63	1		T249	3		T152	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T208	1		T81	13		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T12	4		T50	16		T139	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	3		T138	12		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	3		T14	1		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	4		T145	1		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T18	1		T52	13		T81	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T164	13		T174	1		T263	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T142	1		T165	3		T233	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T137	12		T160	1		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T173	13		T229	9		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T19	1		T140	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T61	3		T137	2		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T151	1		T62	5		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T171	1		T223	13		T187	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T210	11		T296	2		T297	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T298	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T70	4		T71	13		T187	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T16	1		T17	13		T53	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	917	1			T15	23		T97	3		T161	35
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T70	13		T145	3		T163	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T152	12		T104	10		T245	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T208	13		T81	14		T147	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	1		T50	12		T139	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T9	2		T138	16		T231	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	1		T50	1		T70	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T13	1		T145	9		T265	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T18	1		T52	12		T81	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T238	17		T258	13		T219	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T165	7		T233	4		T187	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T223	2		T270	15		T253	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T229	10		T169	5		T245	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T140	6		T165	3		T255	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T61	1		T171	14		T147	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T62	2		T199	12		T47	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T171	5		T223	10		T187	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T297	9		T299	16		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T294	7		T300	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T242	7		T293	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T281	1		T269	1		T301	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T295	1		T291	1		T302	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T146	12		T167	1		T173	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T16	3		T17	1		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1533	1			T12	1		T15	3		T51	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T145	1		T163	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T144	3		T146	1		T63	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T70	20		T208	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T50	16		T139	16		T216	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T147	12		T206	13		T231	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	3		T12	4		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	3		T13	4		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T52	13		T138	5		T38	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T164	13		T38	13		T165	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T18	1		T81	3		T148	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T137	12		T43	1		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T173	13		T169	1		T275	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T160	1		T171	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T61	3		T137	2		T171	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T19	1		T151	1		T62	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T294	3		T300	12		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T293	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T281	14		T269	10		T301	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T291	5		T302	8		T280	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T71	13		T187	3		T222	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T16	1		T17	13		T53	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T15	23		T97	3		T70	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T145	3		T163	12		T142	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T144	2		T152	12		T104	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T70	13		T208	13		T81	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T50	12		T139	16		T216	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T147	10		T231	20		T260	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	1		T12	1		T50	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T9	2		T13	1		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T52	12		T138	6		T169	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T223	2		T265	13		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T18	1		T81	8		T148	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T238	14		T270	15		T219	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T169	5		T221	14		T303	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T140	6		T165	3		T255	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T61	1		T171	19		T147	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T62	2		T199	12		T47	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T12	1		T70	5		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T16	3		T17	14		T53	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T15	26		T51	1		T64	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T70	14		T151	1		T145	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T63	1		T249	1		T152	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T208	14		T81	15		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T12	3		T50	13		T139	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	4		T138	17		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	3		T14	1		T50	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	4		T145	10		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T18	2		T52	13		T81	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T164	1		T174	1		T263	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T142	1		T165	8		T233	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T137	1		T160	1		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T173	2		T229	11		T169	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T19	1		T140	7		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T61	3		T137	1		T171	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T151	1		T62	5		T188	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T171	6		T223	11		T187	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T210	1		T296	2		T297	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T298	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T70	5		T146	11		T71	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T16	1		T139	7		T168	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T51	14		T64	18		T144	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T70	19		T26	1		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T249	2		T152	16		T104	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T81	12		T147	11		T206	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	2		T50	15		T139	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	1		T138	11		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	1		T70	7		T138	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T13	1		T146	9		T168	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T52	12		T81	2		T148	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T164	12		T263	6		T238	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T165	2		T233	3		T218	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T137	11		T223	12		T245	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T173	11		T229	8		T275	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T165	12		T255	12		T155	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T61	1		T137	1		T147	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T62	2		T210	4		T199	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T223	12		T152	10		T104	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T210	10		T297	9		T271	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T294	4		T300	13		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T242	1		T293	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T281	15		T269	11		T301	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T295	1		T291	6		T302	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T146	1		T167	1		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T16	3		T17	14		T53	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T12	1		T15	26		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T145	4		T163	13		T142	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T144	3		T146	1		T63	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T70	14		T208	14		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T50	13		T139	17		T216	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T147	11		T206	1		T231	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	3		T12	3		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	4		T13	4		T145	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T52	13		T138	7		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T164	1		T38	1		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T18	2		T81	9		T148	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T137	1		T43	1		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T173	2		T169	6		T275	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T160	1		T171	1		T140	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T61	3		T137	1		T171	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T19	1		T151	1		T62	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T294	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T242	6		T293	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T302	10		T280	5		T276	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T146	11		T173	11		T71	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T16	1		T139	7		T168	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1198	1			T51	14		T64	18		T70	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T211	10		T239	10		T170	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T144	2		T249	2		T152	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T70	19		T81	12		T26	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T50	15		T139	15		T216	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T147	11		T206	12		T231	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	1		T12	2		T70	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T9	1		T13	1		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T52	12		T138	4		T38	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T164	12		T38	12		T165	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T81	2		T148	13		T165	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T137	11		T245	13		T238	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T173	11		T275	12		T304	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T165	12		T255	12		T155	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T61	1		T137	1		T147	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T62	2		T210	14		T199	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

auto[0]

4077

1

T7

1

T9

1

T12

2