Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25026

1

T1

20

T4

10

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21844

1

T1

20

T4

10

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3182

1

T12

6

T13

5

T17

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19144

1

T1

20

T4

10

T5

20

auto[1]

5882

1

T9

5

T13

5

T15

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T4

10

T5

20

auto[1]

3822

1

T7

2

T9

2

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	307	1			T18	2		T171	15		T39	7
values[0]	12	1			T145	10		T295	1		T305	1
values[1]	716	1			T12	1		T50	2		T151	1
values[2]	627	1			T13	5		T138	28		T141	1
values[3]	526	1			T12	5		T160	1		T144	17
values[4]	3231	1			T15	26		T17	14		T19	1
values[5]	493	1			T208	14		T151	1		T25	1
values[6]	411	1			T7	4		T138	11		T173	12
values[7]	576	1			T14	1		T16	4		T52	25
values[8]	841	1			T137	2		T145	4		T139	40
values[9]	1055	1			T9	5		T50	28		T53	13
minimum	16231	1			T1	20		T4	10		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	622	1			T12	1		T50	2		T151	1
values[1]	665	1			T13	5		T138	28		T171	1
values[2]	657	1			T12	5		T160	1		T144	17
values[3]	3006	1			T15	26		T17	14		T19	1
values[4]	548	1			T208	14		T151	1		T138	11
values[5]	562	1			T7	4		T173	12		T26	4
values[6]	489	1			T14	1		T16	4		T52	25
values[7]	766	1			T137	2		T145	4		T139	40
values[8]	1109	1			T9	5		T18	2		T50	28
values[9]	122	1			T151	1		T171	15		T39	7
minimum	16480	1			T1	20		T4	10		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

4077

1

T7

1

T9

1

T12

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T50	1		T145	1		T173	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	1		T151	1		T249	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T171	1		T141	1		T165	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	4		T138	12		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T144	3		T63	1		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	4		T160	1		T144	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1670	1			T15	3		T19	1		T51	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T17	1		T70	20		T38	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T208	1		T138	5		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T151	1		T38	14		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	3		T173	12		T152	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T26	3		T71	14		T211	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	1		T16	3		T52	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T70	6		T146	12		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T137	2		T145	1		T139	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T139	16		T171	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T9	3		T61	3		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T18	1		T50	16		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T39	5		T170	1		T306	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T151	1		T171	1		T226	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16204	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T81	3		T62	5		T206	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T50	1		T145	9		T147	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T207	5		T152	19		T155	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T165	3		T153	1		T217	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	1		T138	16		T148	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T144	2		T216	8		T214	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	1		T144	2		T166	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T15	23		T97	3		T81	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T17	13		T70	13		T142	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T208	13		T138	6		T169	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T170	4		T219	14		T220	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	1		T152	15		T153	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T26	1		T71	13		T224	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	1		T52	12		T223	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T70	4		T207	2		T215	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T145	3		T165	7		T225	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T139	16		T171	5		T140	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T9	2		T61	1		T223	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T18	1		T50	12		T53	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T39	2		T170	1		T306	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T171	14		T226	11		T307	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	1		T12	3		T16	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T81	8		T62	2		T199	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T39	5		T43	1		T75	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T18	1		T171	1		T308	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T145	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T295	1		T305	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T50	1		T173	1		T147	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	1		T151	1		T81	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T165	13		T210	5		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	4		T138	12		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T144	3		T171	1		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	4		T160	1		T144	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1714	1			T15	3		T19	1		T51	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T17	1		T70	20		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T208	1		T25	1		T210	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T151	1		T38	14		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	3		T138	5		T173	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T43	1		T26	3		T211	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	1		T16	3		T52	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T70	6		T146	12		T71	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T137	2		T145	1		T139	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T139	16		T171	1		T164	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T9	3		T61	3		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T50	16		T53	1		T70	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T39	2		T170	1		T212	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T18	1		T171	14		T308	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T145	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T50	1		T147	2		T229	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T81	8		T62	2		T199	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T165	3		T217	1		T226	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	1		T138	16		T148	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T144	2		T214	14		T153	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T12	1		T144	2		T231	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T15	23		T97	3		T81	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T17	13		T70	13		T166	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T208	13		T169	5		T209	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T142	6		T170	4		T220	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T7	1		T138	6		T218	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T26	1		T222	2		T219	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T16	1		T52	12		T223	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T70	4		T71	13		T224	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T145	3		T165	7		T233	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T139	16		T171	5		T187	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T9	2		T61	1		T223	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T50	12		T53	12		T70	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T50	2		T145	10		T173	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T151	1		T249	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T171	1		T141	1		T165	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	4		T138	17		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T144	3		T63	1		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	3		T160	1		T144	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T15	26		T19	1		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T17	14		T70	14		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T208	14		T138	7		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T151	1		T38	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	3		T173	1		T152	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T26	3		T71	14		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	1		T16	3		T52	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T70	5		T146	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T137	1		T145	4		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T139	17		T171	6		T140	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T9	4		T61	3		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T18	2		T50	13		T53	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T39	3		T170	2		T306	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T151	1		T171	15		T226	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16301	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T81	9		T62	5		T206	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T147	5		T228	17		T229	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T249	2		T207	4		T152	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T165	12		T210	4		T234	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	1		T138	11		T148	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T144	2		T216	9		T168	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	2		T144	9		T146	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T51	14		T64	18		T137	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T70	19		T38	12		T152	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T138	4		T210	10		T218	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T38	13		T165	8		T170	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	1		T173	11		T152	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T26	1		T71	13		T211	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T16	1		T52	12		T206	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T70	5		T146	11		T261	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T137	1		T139	7		T168	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T139	15		T164	12		T240	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T9	1		T61	1		T239	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T50	15		T70	7		T187	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T39	4		T297	13		T309	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T226	13		T307	7		T290	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T252	15		T237	13		T310	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T81	2		T62	2		T206	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T39	3		T43	1		T75	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T18	2		T171	15		T308	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T145	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T295	1		T305	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T50	2		T173	1		T147	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	1		T151	1		T81	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T165	4		T210	1		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	4		T138	17		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T144	3		T171	1		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	3		T160	1		T144	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T15	26		T19	1		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T17	14		T70	14		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T208	14		T25	1		T210	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T151	1		T38	1		T142	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	3		T138	7		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T43	1		T26	3		T211	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	1		T16	3		T52	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T70	5		T146	1		T71	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T137	1		T145	4		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T139	17		T171	6		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T9	4		T61	3		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T50	13		T53	13		T70	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T39	4		T212	18		T283	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T308	14		T226	13		T311	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T147	5		T228	17		T229	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T81	2		T62	2		T206	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T165	12		T210	4		T261	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	1		T138	11		T148	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T144	2		T234	20		T157	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	2		T144	9		T173	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T51	14		T64	18		T137	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T70	19		T146	9		T38	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T210	10		T230	11		T263	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T38	13		T165	8		T170	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	1		T138	4		T173	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T26	1		T211	10		T219	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T16	1		T52	12		T223	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T70	5		T146	11		T71	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T137	1		T139	7		T168	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T139	15		T164	12		T237	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T9	1		T61	1		T239	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T50	15		T70	7		T240	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

auto[0]

4077

1

T7

1

T9

1

T12

2