Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25026

1

T1

20

T4

10

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21467

1

T1

20

T4

10

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3559

1

T16

4

T18

2

T50

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19123

1

T1

20

T4

10

T5

20

auto[1]

5903

1

T9

5

T12

6

T15

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T4

10

T5

20

auto[1]

3822

1

T7

2

T9

2

T12

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	16	1			T312	1		T313	3		T289	2
values[0]	24	1			T141	1		T207	3		T314	10
values[1]	601	1			T18	2		T137	12		T70	14
values[2]	783	1			T50	2		T208	14		T146	10
values[3]	492	1			T16	4		T151	2		T140	7
values[4]	773	1			T70	33		T160	1		T63	1
values[5]	649	1			T7	4		T9	5		T14	1
values[6]	737	1			T13	5		T138	28		T139	32
values[7]	746	1			T17	14		T53	13		T61	4
values[8]	562	1			T12	5		T52	25		T160	1
values[9]	3412	1			T12	1		T15	26		T19	1
minimum	16231	1			T1	20		T4	10		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	898	1			T18	2		T137	12		T70	14
values[1]	592	1			T16	4		T50	2		T151	2
values[2]	701	1			T70	33		T216	18		T147	8
values[3]	673	1			T160	1		T140	7		T173	1
values[4]	595	1			T7	4		T9	5		T14	1
values[5]	748	1			T13	5		T61	4		T145	10
values[6]	3014	1			T15	26		T17	14		T51	15
values[7]	508	1			T12	5		T52	25		T81	27
values[8]	877	1			T12	1		T19	1		T70	10
values[9]	163	1			T81	11		T168	9		T166	31
minimum	16257	1			T1	20		T4	10		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

4077

1

T7

1

T9

1

T12

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T208	1		T141	2		T39	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T18	1		T137	12		T70	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T50	1		T151	2		T206	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T16	3		T146	10		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T147	6		T164	13		T188	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T70	20		T216	10		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T160	1		T173	1		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T140	1		T211	19		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	3		T9	3		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T50	16		T145	1		T138	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	4		T139	17		T38	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T61	3		T145	1		T138	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1591	1			T15	3		T17	1		T51	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T137	2		T171	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	4		T52	13		T81	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T141	1		T26	3		T165	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	1		T19	1		T70	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T146	13		T171	1		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T81	3		T251	1		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T168	9		T166	15		T239	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16147	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T234	7		T295	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T208	13		T39	2		T169	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T18	1		T70	6		T148	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T50	1		T170	4		T252	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T16	1		T209	8		T240	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T147	2		T270	15		T215	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T70	13		T216	8		T233	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T75	6		T214	14		T153	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T140	6		T104	22		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T7	1		T9	2		T209	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T50	12		T145	1		T138	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	1		T139	16		T229	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T61	1		T145	9		T138	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T15	23		T17	13		T53	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T171	14		T163	12		T199	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	1		T52	12		T81	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T26	1		T28	2		T215	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T70	4		T144	4		T145	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T230	6		T156	3		T183	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T81	8		T238	11		T268	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T166	16		T315	10		T316	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T7	1		T12	3		T16	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T312	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T313	2		T289	1		T317	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T141	1		T207	1		T314	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T318	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T141	1		T39	5		T206	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T18	1		T137	12		T70	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T50	1		T208	1		T206	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T146	10		T210	19		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T151	2		T188	1		T210	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T16	3		T140	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T160	1		T147	6		T164	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T70	20		T63	1		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T7	3		T9	3		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T50	16		T145	1		T138	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	4		T139	16		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T138	12		T173	12		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T17	1		T53	1		T62	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T61	3		T137	2		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	4		T52	13		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T171	1		T38	2		T223	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1691	1			T12	1		T15	3		T19	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T146	13		T171	1		T168	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16138	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T313	1		T289	1		T317	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T207	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T318	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T39	2		T169	3		T231	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T18	1		T70	6		T148	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T50	1		T208	13		T170	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T209	8		T155	7		T230	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T270	15		T215	3		T220	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	1		T140	6		T216	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T147	2		T153	10		T218	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T70	13		T233	4		T187	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T7	1		T9	2		T75	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T50	12		T145	1		T138	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	1		T139	16		T229	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T138	16		T165	3		T47	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T17	13		T53	12		T62	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T61	1		T145	9		T163	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	1		T52	12		T252	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T171	14		T223	2		T207	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1091	1			T15	23		T97	3		T70	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T26	1		T166	16		T230	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	1		T12	3		T16	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T208	14		T141	2		T39	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T18	2		T137	1		T70	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T50	2		T151	2		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T16	3		T146	1		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T147	3		T164	1		T188	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T70	14		T216	9		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T160	1		T173	1		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T140	7		T211	2		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	3		T9	4		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T50	13		T145	2		T138	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	4		T139	18		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T61	3		T145	10		T138	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T15	26		T17	14		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T137	1		T171	15		T163	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	3		T52	13		T81	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T141	1		T26	3		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	1		T19	1		T70	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T146	2		T171	1		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T81	9		T251	1		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T168	1		T166	17		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16241	1			T1	20		T4	10		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T234	1		T295	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T39	4		T206	12		T152	26
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T137	11		T70	7		T148	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T206	12		T210	10		T170	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T16	1		T146	9		T38	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T147	5		T164	12		T215	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T70	19		T216	9		T233	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T75	4		T153	11		T218	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T211	17		T104	21		T156	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T7	1		T9	1		T187	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T50	15		T138	4		T139	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	1		T139	15		T38	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T61	1		T138	11		T173	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T51	14		T64	18		T62	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T137	1		T38	1		T199	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	2		T52	12		T81	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T26	1		T165	8		T223	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T70	5		T144	11		T165	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T146	11		T230	7		T156	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T81	2		T238	4		T319	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T168	8		T166	14		T239	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T231	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T234	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T312	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T313	2		T289	2		T317	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T141	1		T207	3		T314	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T318	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T141	1		T39	3		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T18	2		T137	1		T70	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T50	2		T208	14		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T146	1		T210	1		T209	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T151	2		T188	1		T210	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T16	3		T140	7		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T160	1		T147	3		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T70	14		T63	1		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	3		T9	4		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T50	13		T145	2		T138	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	4		T139	17		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T138	17		T173	1		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T17	14		T53	13		T62	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T61	3		T137	1		T145	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	3		T52	13		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T171	15		T38	1		T223	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1460	1			T12	1		T15	26		T19	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T146	2		T171	1		T168	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16231	1			T1	20		T4	10		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T313	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T314	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T318	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	4		T206	12		T231	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T137	11		T70	7		T148	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T206	12		T170	1		T252	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T146	9		T210	18		T261	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T210	10		T215	4		T247	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T16	1		T216	9		T38	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T147	5		T164	12		T153	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T70	19		T233	3		T207	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T7	1		T9	1		T75	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T50	15		T138	4		T139	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	1		T139	15		T229	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T138	11		T173	11		T165	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T62	2		T173	11		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T61	1		T137	1		T168	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	2		T52	12		T168	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T38	1		T223	12		T207	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T51	14		T64	18		T70	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T146	11		T168	8		T26	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20949

1

T1

20

T4

10

T5

20

auto[1]

auto[0]

4077

1

T7

1

T9

1

T12

2