Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5747	1			T2	20		T3	20		T4	16
testmodes[AdcCtrlTestmodeNormal]	4724	1			T4	3		T7	7		T8	2
testmodes[AdcCtrlTestmodeLowpower]	4922	1			T5	1		T6	14		T8	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2999	1			T2	19		T3	19		T4	13
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1487	1			T4	3		T7	5		T49	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1151	1			T8	1		T57	11		T58	22
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1415	1			T4	2		T7	4		T8	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1715	1			T7	2		T64	3		T12	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1270	1			T8	1		T9	1		T12	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1212	1			T9	1		T16	1		T52	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1184	1			T8	1		T12	1		T52	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2262	1			T6	13		T51	9		T60	9