Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.70 99.07 96.67 100.00 100.00 98.82 98.33 90.99


Total tests in report: 919
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
73.81 73.81 97.06 97.06 80.98 80.98 87.44 87.44 56.76 56.76 95.28 95.28 85.81 85.81 13.33 13.33 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.327231827
80.76 6.95 98.48 1.43 86.54 5.56 94.79 7.35 81.08 24.32 97.52 2.23 87.81 2.00 19.09 5.76 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3663094211
83.59 2.83 98.48 0.00 86.54 0.00 94.79 0.00 100.00 18.92 97.52 0.00 87.81 0.00 20.01 0.92 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.600727014
85.99 2.40 98.76 0.28 92.67 6.13 94.79 0.00 100.00 0.00 98.20 0.68 89.98 2.17 27.53 7.51 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.1155279543
87.19 1.20 98.76 0.00 92.67 0.00 94.79 0.00 100.00 0.00 98.20 0.00 90.15 0.17 35.74 8.21 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.2593898149
88.21 1.03 98.76 0.00 92.67 0.00 94.79 0.00 100.00 0.00 98.20 0.00 90.15 0.00 42.92 7.19 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1960262355
89.11 0.90 98.76 0.00 92.67 0.00 94.79 0.00 100.00 0.00 98.20 0.00 90.15 0.00 49.21 6.29 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.1197597392
89.91 0.80 98.76 0.00 93.78 1.11 95.38 0.59 100.00 0.00 98.32 0.12 90.15 0.00 53.01 3.79 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.1241991076
90.64 0.73 98.76 0.00 93.78 0.00 95.38 0.00 100.00 0.00 98.32 0.00 94.16 4.01 54.08 1.07 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.595187627
91.30 0.66 98.76 0.00 93.78 0.00 95.38 0.00 100.00 0.00 98.32 0.00 94.32 0.17 58.55 4.47 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.2101781502
91.83 0.53 98.76 0.00 93.87 0.08 95.38 0.00 100.00 0.00 98.32 0.00 94.32 0.00 62.19 3.64 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.3428260821
92.33 0.49 98.88 0.12 94.32 0.45 96.80 1.42 100.00 0.00 98.57 0.25 94.99 0.67 62.74 0.55 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.1335722438
92.79 0.46 98.88 0.00 95.76 1.44 97.27 0.47 100.00 0.00 98.63 0.06 95.66 0.67 63.31 0.57 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.939473860
93.23 0.44 98.88 0.00 95.76 0.00 97.27 0.00 100.00 0.00 98.63 0.00 95.66 0.00 66.38 3.07 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.1828261983
93.63 0.40 98.88 0.00 95.76 0.00 97.27 0.00 100.00 0.00 98.63 0.00 95.99 0.33 68.85 2.47 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.2118321654
94.01 0.38 98.92 0.03 95.88 0.12 99.41 2.13 100.00 0.00 98.70 0.06 96.16 0.17 68.98 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.36099642
94.32 0.31 98.92 0.00 95.88 0.00 99.41 0.00 100.00 0.00 98.70 0.00 96.16 0.00 71.15 2.17 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.2622548252
94.61 0.30 98.92 0.00 95.97 0.08 99.76 0.36 100.00 0.00 98.70 0.00 96.33 0.17 72.62 1.47 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3769853324
94.86 0.24 98.92 0.00 95.97 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.33 0.00 74.32 1.70 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.273933641
95.07 0.22 98.98 0.06 96.13 0.16 99.76 0.00 100.00 0.00 98.82 0.12 97.50 1.17 74.32 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.726036901
95.28 0.20 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.50 0.00 75.74 1.42 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3050862545
95.48 0.20 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.50 0.00 77.16 1.42 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.1592695296
95.66 0.19 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.50 0.00 78.46 1.30 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.1113251725
95.83 0.16 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.50 0.00 79.61 1.15 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.3522070097
95.97 0.14 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.33 80.28 0.67 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.2073464822
96.10 0.13 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 81.21 0.92 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.3852455202
96.22 0.11 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 82.01 0.80 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.1259129942
96.31 0.10 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.00 0.17 82.51 0.50 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3266422544
96.40 0.09 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.00 0.00 83.13 0.62 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.4056717517
96.49 0.09 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.00 0.00 83.73 0.60 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.2090149175
96.56 0.07 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.00 0.00 84.25 0.52 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.3318574864
96.63 0.07 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.00 0.00 84.73 0.47 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.2206017200
96.70 0.07 98.98 0.00 96.13 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.00 0.00 85.20 0.47 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.3612095827
96.76 0.06 99.07 0.09 96.25 0.12 100.00 0.24 100.00 0.00 98.82 0.00 98.00 0.00 85.20 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.1932512085
96.82 0.06 99.07 0.00 96.46 0.21 100.00 0.00 100.00 0.00 98.82 0.00 98.00 0.00 85.43 0.22 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2181351685
96.88 0.05 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.00 0.00 85.80 0.37 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.285163477
96.93 0.05 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.17 86.00 0.20 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.1545158252
96.97 0.04 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 86.27 0.27 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all.458192914
97.01 0.04 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 86.55 0.27 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.4111425279
97.04 0.04 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 86.80 0.25 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.2935416204
97.08 0.04 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 87.05 0.25 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt.3803844215
97.12 0.04 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 87.30 0.25 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup.3362864273
97.15 0.03 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 87.52 0.22 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.4238680581
97.18 0.03 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 87.72 0.20 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup.4161581692
97.20 0.02 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 87.90 0.17 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.696698470
97.23 0.02 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 88.07 0.17 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.829999864
97.25 0.02 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.17 88.07 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1139391189
97.27 0.02 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.22 0.15 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.825462128
97.29 0.02 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.37 0.15 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.3061805301
97.31 0.02 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.50 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.4042303213
97.33 0.02 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.62 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.4167688674
97.35 0.02 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.74 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.1008146602
97.36 0.02 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.87 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.1969767277
97.38 0.02 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.99 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.3970438763
97.40 0.01 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.09 0.10 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.646195756
97.41 0.01 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.19 0.10 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.3666468718
97.42 0.01 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.29 0.10 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.4103464115
97.44 0.01 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.39 0.10 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.696954738
97.45 0.01 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.49 0.10 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.2247182071
97.47 0.01 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.59 0.10 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.3358891608
97.48 0.01 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.69 0.10 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.2915331575
97.49 0.01 99.07 0.00 96.54 0.08 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.69 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2606744874
97.50 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.77 0.07 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2911343013
97.52 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.84 0.07 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.1695985663
97.53 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.92 0.07 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.46851042
97.54 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.99 0.07 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.1553395707
97.55 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.07 0.07 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.501046149
97.55 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.12 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.1367754570
97.56 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.17 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.3099854933
97.57 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.22 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.2605165248
97.58 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.27 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.3603922432
97.58 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.32 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.27768107
97.59 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.37 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3601123765
97.60 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.42 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.3887694892
97.60 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.47 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.850030674
97.61 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.52 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled.2683552349
97.62 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.57 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3498013562
97.63 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.62 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt.2982567313
97.63 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.67 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup.308030568
97.64 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.72 0.05 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.3799822653
97.65 0.01 99.07 0.00 96.58 0.04 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.924684861
97.65 0.01 99.07 0.00 96.62 0.04 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3228532358
97.66 0.01 99.07 0.00 96.67 0.04 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.1185155308
97.66 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.74 0.02 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1377660586
97.66 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.77 0.02 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.3744073577
97.67 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.79 0.02 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4090949108
97.67 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.82 0.02 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.1660004818
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.84 0.02 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.3396001614
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.87 0.02 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.4187799748
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.89 0.02 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.3316458977
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.92 0.02 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.2720527473
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.94 0.02 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.3215369465
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.97 0.02 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_fsm_reset.2830018637
97.70 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.99 0.02 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_fsm_reset.3563209876

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1196713385
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.962504263
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1510910813
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.4288243346
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.775724227
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2455928831
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.32905781
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1753266524
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2708537187
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3204227951
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.2050064560
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.4053283166
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1856086318
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.415870527
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3864178935
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2047786209
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.2471735844
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.201667275
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2219938358
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.898661028
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2867944123
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2243419788
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.925345790
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3161796312
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.390785994
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2314344972
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4077285719
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2026039169
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.2037048538
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2156849591
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1455812345
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3531563933
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.845283150
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.391685307
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2839209050
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1154592886
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1554734249
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3087858281
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1903128167
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3740514560
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2747250473
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2521156507
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3637645387
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1905287286
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.257037111
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3237287352
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.890903684
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2415246898
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4221716385
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.246944775
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1302947692
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3885823113
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.1705251271
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.519442667
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1521296332
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2056748564
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1187383295
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1441035486
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.1286511
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.457748074
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2214198134
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3347427706
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1268759042
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1600337365
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.3261238805
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2032020612
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.877443356
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1206414744
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.572373286
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3859396659
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2604694810
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.872962974
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3207472550
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2011868505
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3823956955
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1594606551
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2198825403
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3785369775
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.71162938
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4057336014
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3320899943
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.2079403252
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.335886399
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.1000775811
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.1039849783
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.730289000
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.1239280097
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.917606903
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.1329826096
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.1542379075
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.2190515600
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1040591034
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.4165646928
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2725540583
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3612883893
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3663360327
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.946850235
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3963411584
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3885625297
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3929193987
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.2273795852
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.1109636321
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.722649411
/workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.316216517
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Total test records in report: 919
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.1932512085 Sep 18 06:32:23 AM UTC 24 Sep 18 06:32:25 AM UTC 24 558605958 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.715901615 Sep 18 06:32:20 AM UTC 24 Sep 18 06:32:27 AM UTC 24 5782569260 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.1293042386 Sep 18 06:32:25 AM UTC 24 Sep 18 06:32:28 AM UTC 24 5754010948 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.3210186605 Sep 18 06:32:21 AM UTC 24 Sep 18 06:32:29 AM UTC 24 5292993279 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.1335722438 Sep 18 06:33:47 AM UTC 24 Sep 18 06:38:57 AM UTC 24 259938976323 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.1185155308 Sep 18 06:32:21 AM UTC 24 Sep 18 06:32:31 AM UTC 24 30554359606 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.4020145696 Sep 18 06:32:31 AM UTC 24 Sep 18 06:32:34 AM UTC 24 325003924 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.265222761 Sep 18 06:32:29 AM UTC 24 Sep 18 06:32:36 AM UTC 24 4807409226 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.327231827 Sep 18 06:32:22 AM UTC 24 Sep 18 06:32:42 AM UTC 24 5551616849 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3050862545 Sep 18 06:32:30 AM UTC 24 Sep 18 06:32:43 AM UTC 24 6288419693 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.36099642 Sep 18 06:32:23 AM UTC 24 Sep 18 06:32:45 AM UTC 24 7891037381 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.3929913840 Sep 18 06:32:32 AM UTC 24 Sep 18 06:32:46 AM UTC 24 5723413778 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.4252767372 Sep 18 06:32:30 AM UTC 24 Sep 18 06:32:46 AM UTC 24 8457235261 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.2117841403 Sep 18 06:32:25 AM UTC 24 Sep 18 06:32:49 AM UTC 24 162880653893 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.467819610 Sep 18 06:32:54 AM UTC 24 Sep 18 06:32:56 AM UTC 24 302400577 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.1710104897 Sep 18 06:32:45 AM UTC 24 Sep 18 06:32:57 AM UTC 24 3445932711 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.3501547947 Sep 18 06:32:55 AM UTC 24 Sep 18 06:33:03 AM UTC 24 5853643416 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.1468228630 Sep 18 06:32:46 AM UTC 24 Sep 18 06:33:04 AM UTC 24 21972625322 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.4170066104 Sep 18 06:32:50 AM UTC 24 Sep 18 06:33:11 AM UTC 24 7310450131 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.3294104068 Sep 18 06:32:29 AM UTC 24 Sep 18 06:33:14 AM UTC 24 21107318652 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.644262928 Sep 18 06:33:11 AM UTC 24 Sep 18 06:33:22 AM UTC 24 5388907618 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3663094211 Sep 18 06:32:46 AM UTC 24 Sep 18 06:33:24 AM UTC 24 106938930534 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.185780222 Sep 18 06:33:28 AM UTC 24 Sep 18 06:33:35 AM UTC 24 7893219260 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.1046093804 Sep 18 06:33:36 AM UTC 24 Sep 18 06:33:38 AM UTC 24 373831593 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.125619440 Sep 18 06:33:15 AM UTC 24 Sep 18 06:33:44 AM UTC 24 34511965036 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2401709327 Sep 18 06:33:23 AM UTC 24 Sep 18 06:33:46 AM UTC 24 2556373139 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.604128591 Sep 18 06:33:36 AM UTC 24 Sep 18 06:34:04 AM UTC 24 5976762704 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3769853324 Sep 18 06:32:37 AM UTC 24 Sep 18 06:34:09 AM UTC 24 162688045355 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.888984326 Sep 18 06:32:25 AM UTC 24 Sep 18 06:34:18 AM UTC 24 160173440977 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.1777460753 Sep 18 06:34:20 AM UTC 24 Sep 18 06:34:23 AM UTC 24 3686327958 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.778826553 Sep 18 06:33:03 AM UTC 24 Sep 18 06:34:53 AM UTC 24 199840828875 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.3389466735 Sep 18 06:34:24 AM UTC 24 Sep 18 06:35:02 AM UTC 24 35345628207 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.62148287 Sep 18 06:35:01 AM UTC 24 Sep 18 06:35:03 AM UTC 24 419307073 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.4116651183 Sep 18 06:35:02 AM UTC 24 Sep 18 06:35:10 AM UTC 24 6025402319 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1967494602 Sep 18 06:34:52 AM UTC 24 Sep 18 06:35:12 AM UTC 24 6557771207 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.1155279543 Sep 18 06:32:43 AM UTC 24 Sep 18 06:35:15 AM UTC 24 350206065116 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.3977791308 Sep 18 06:32:47 AM UTC 24 Sep 18 06:35:18 AM UTC 24 184878227550 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.967057441 Sep 18 06:34:57 AM UTC 24 Sep 18 06:35:29 AM UTC 24 7881160500 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.2554646331 Sep 18 06:32:56 AM UTC 24 Sep 18 06:35:31 AM UTC 24 161909151880 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.59111238 Sep 18 06:32:20 AM UTC 24 Sep 18 06:35:38 AM UTC 24 324390419337 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.1367754570 Sep 18 06:32:20 AM UTC 24 Sep 18 06:35:43 AM UTC 24 337739776935 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.952473891 Sep 18 06:35:39 AM UTC 24 Sep 18 06:35:53 AM UTC 24 3016027007 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.415565297 Sep 18 06:32:37 AM UTC 24 Sep 18 06:35:55 AM UTC 24 168207845791 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.2412994262 Sep 18 06:33:39 AM UTC 24 Sep 18 06:35:56 AM UTC 24 165771338327 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.1462478104 Sep 18 06:35:55 AM UTC 24 Sep 18 06:35:58 AM UTC 24 420642108 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.3811958504 Sep 18 06:35:56 AM UTC 24 Sep 18 06:36:11 AM UTC 24 5679019993 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.1241991076 Sep 18 06:32:26 AM UTC 24 Sep 18 06:36:16 AM UTC 24 330095926052 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3850818138 Sep 18 06:35:54 AM UTC 24 Sep 18 06:36:18 AM UTC 24 3418897596 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.2548260200 Sep 18 06:35:44 AM UTC 24 Sep 18 06:36:30 AM UTC 24 28364348316 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.825462128 Sep 18 06:32:44 AM UTC 24 Sep 18 06:36:46 AM UTC 24 159867084745 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.2199149234 Sep 18 06:36:46 AM UTC 24 Sep 18 06:36:55 AM UTC 24 2856724169 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.680429937 Sep 18 06:33:41 AM UTC 24 Sep 18 06:37:01 AM UTC 24 163971572560 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.3919467528 Sep 18 06:32:55 AM UTC 24 Sep 18 06:37:04 AM UTC 24 487569641315 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2071847668 Sep 18 06:35:15 AM UTC 24 Sep 18 06:37:15 AM UTC 24 169751643347 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2561001028 Sep 18 06:35:20 AM UTC 24 Sep 18 06:37:16 AM UTC 24 398208569551 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.3529492182 Sep 18 06:37:16 AM UTC 24 Sep 18 06:37:18 AM UTC 24 523710921 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.501046149 Sep 18 06:37:03 AM UTC 24 Sep 18 06:37:22 AM UTC 24 3521669580 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.957798596 Sep 18 06:37:17 AM UTC 24 Sep 18 06:37:25 AM UTC 24 5841480787 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.2610319597 Sep 18 06:32:26 AM UTC 24 Sep 18 06:37:34 AM UTC 24 622228753126 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.2073464822 Sep 18 06:33:03 AM UTC 24 Sep 18 06:37:41 AM UTC 24 604105559233 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.1659294287 Sep 18 06:32:33 AM UTC 24 Sep 18 06:37:50 AM UTC 24 330436901201 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.1173113897 Sep 18 06:35:58 AM UTC 24 Sep 18 06:37:53 AM UTC 24 162406947085 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.2897811527 Sep 18 06:34:54 AM UTC 24 Sep 18 06:38:10 AM UTC 24 173354417926 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.2480887257 Sep 18 06:32:55 AM UTC 24 Sep 18 06:38:19 AM UTC 24 326541718691 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.3292150864 Sep 18 06:36:55 AM UTC 24 Sep 18 06:38:23 AM UTC 24 43189731682 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.819772238 Sep 18 06:38:20 AM UTC 24 Sep 18 06:38:24 AM UTC 24 4822689580 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.3174481879 Sep 18 06:32:35 AM UTC 24 Sep 18 06:38:45 AM UTC 24 321621216379 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2339869879 Sep 18 06:32:26 AM UTC 24 Sep 18 06:39:08 AM UTC 24 167491282689 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.3705353155 Sep 18 06:39:09 AM UTC 24 Sep 18 06:39:12 AM UTC 24 343827575 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.1171584931 Sep 18 06:37:25 AM UTC 24 Sep 18 06:39:13 AM UTC 24 161971024884 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.467826354 Sep 18 06:38:46 AM UTC 24 Sep 18 06:39:16 AM UTC 24 25077351488 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.2512761851 Sep 18 06:39:13 AM UTC 24 Sep 18 06:39:19 AM UTC 24 5764602984 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.3428260821 Sep 18 06:32:28 AM UTC 24 Sep 18 06:39:27 AM UTC 24 572258027170 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.2144494122 Sep 18 06:35:04 AM UTC 24 Sep 18 06:39:31 AM UTC 24 490000529360 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.3522070097 Sep 18 06:32:21 AM UTC 24 Sep 18 06:39:36 AM UTC 24 343261735043 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.3061805301 Sep 18 06:33:19 AM UTC 24 Sep 18 06:39:56 AM UTC 24 74463835641 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.4137612672 Sep 18 06:39:56 AM UTC 24 Sep 18 06:40:02 AM UTC 24 3726002623 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.1545158252 Sep 18 06:35:18 AM UTC 24 Sep 18 06:40:22 AM UTC 24 378448607270 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.1316857444 Sep 18 06:38:24 AM UTC 24 Sep 18 06:40:38 AM UTC 24 37100375895 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3095098913 Sep 18 06:32:58 AM UTC 24 Sep 18 06:40:40 AM UTC 24 324844397856 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.1011966356 Sep 18 06:40:41 AM UTC 24 Sep 18 06:40:43 AM UTC 24 366728813 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.3529644392 Sep 18 06:38:11 AM UTC 24 Sep 18 06:40:46 AM UTC 24 364789573498 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2604812670 Sep 18 06:40:26 AM UTC 24 Sep 18 06:40:47 AM UTC 24 16312720470 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.1113251725 Sep 18 06:33:05 AM UTC 24 Sep 18 06:40:54 AM UTC 24 371190375896 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3236487223 Sep 18 06:36:17 AM UTC 24 Sep 18 06:40:55 AM UTC 24 333413740602 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.600727014 Sep 18 06:32:46 AM UTC 24 Sep 18 06:41:05 AM UTC 24 123598363324 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.2434987557 Sep 18 06:34:27 AM UTC 24 Sep 18 06:41:05 AM UTC 24 102466600337 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.2605165248 Sep 18 06:32:22 AM UTC 24 Sep 18 06:41:06 AM UTC 24 252622687442 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.2760647251 Sep 18 06:40:44 AM UTC 24 Sep 18 06:41:11 AM UTC 24 5821571094 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.2673466350 Sep 18 06:39:19 AM UTC 24 Sep 18 06:41:17 AM UTC 24 170229824378 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.1966656742 Sep 18 06:40:02 AM UTC 24 Sep 18 06:41:19 AM UTC 24 26927750589 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.1175341309 Sep 18 06:41:17 AM UTC 24 Sep 18 06:41:26 AM UTC 24 4400929428 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.62541490 Sep 18 06:33:44 AM UTC 24 Sep 18 06:41:30 AM UTC 24 330540279829 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.3094794859 Sep 18 06:33:25 AM UTC 24 Sep 18 06:41:33 AM UTC 24 125779069178 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2826139510 Sep 18 06:39:28 AM UTC 24 Sep 18 06:41:39 AM UTC 24 162876758027 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2302204914 Sep 18 06:32:20 AM UTC 24 Sep 18 06:41:42 AM UTC 24 162285236417 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.703855148 Sep 18 06:41:40 AM UTC 24 Sep 18 06:41:43 AM UTC 24 389522724 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.3099854933 Sep 18 06:32:21 AM UTC 24 Sep 18 06:41:57 AM UTC 24 127035006550 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.4228245241 Sep 18 06:41:43 AM UTC 24 Sep 18 06:42:08 AM UTC 24 5823386197 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1891726329 Sep 18 06:41:31 AM UTC 24 Sep 18 06:42:09 AM UTC 24 167126740523 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.1419343573 Sep 18 06:38:58 AM UTC 24 Sep 18 06:42:14 AM UTC 24 324927760759 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.1548823926 Sep 18 06:40:55 AM UTC 24 Sep 18 06:42:19 AM UTC 24 159183107095 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.3617388351 Sep 18 06:32:29 AM UTC 24 Sep 18 06:42:31 AM UTC 24 110302717194 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.221456205 Sep 18 06:41:20 AM UTC 24 Sep 18 06:42:40 AM UTC 24 45011499212 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.4057716843 Sep 18 06:35:53 AM UTC 24 Sep 18 06:42:45 AM UTC 24 93902391246 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.4068700174 Sep 18 06:42:47 AM UTC 24 Sep 18 06:43:05 AM UTC 24 4262952042 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.4111425279 Sep 18 06:34:19 AM UTC 24 Sep 18 06:43:17 AM UTC 24 212759471879 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.1592695296 Sep 18 06:33:06 AM UTC 24 Sep 18 06:43:25 AM UTC 24 351739669496 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.2772470393 Sep 18 06:37:23 AM UTC 24 Sep 18 06:43:29 AM UTC 24 329308899536 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.1048875891 Sep 18 06:36:12 AM UTC 24 Sep 18 06:43:38 AM UTC 24 161355997344 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2911343013 Sep 18 06:43:26 AM UTC 24 Sep 18 06:43:39 AM UTC 24 7480031282 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.3975691769 Sep 18 06:43:38 AM UTC 24 Sep 18 06:43:40 AM UTC 24 484574258 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.2915331575 Sep 18 06:39:31 AM UTC 24 Sep 18 06:43:48 AM UTC 24 363932306700 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.3115096539 Sep 18 06:43:39 AM UTC 24 Sep 18 06:43:52 AM UTC 24 5753116746 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2441868659 Sep 18 06:42:19 AM UTC 24 Sep 18 06:43:54 AM UTC 24 192791398553 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.4046190122 Sep 18 06:40:47 AM UTC 24 Sep 18 06:44:15 AM UTC 24 163666629340 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.3279877870 Sep 18 06:36:15 AM UTC 24 Sep 18 06:44:17 AM UTC 24 169302544832 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.2565473226 Sep 18 06:42:15 AM UTC 24 Sep 18 06:44:31 AM UTC 24 185623816253 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2101449769 Sep 18 06:37:02 AM UTC 24 Sep 18 06:44:54 AM UTC 24 88398053649 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2638956071 Sep 18 06:40:56 AM UTC 24 Sep 18 06:44:54 AM UTC 24 333631232985 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.2593898149 Sep 18 06:39:44 AM UTC 24 Sep 18 06:44:57 AM UTC 24 510322296242 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.625695209 Sep 18 06:43:06 AM UTC 24 Sep 18 06:44:57 AM UTC 24 28104605511 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.3535082035 Sep 18 06:44:55 AM UTC 24 Sep 18 06:44:59 AM UTC 24 3715614362 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1960262355 Sep 18 06:32:21 AM UTC 24 Sep 18 06:45:19 AM UTC 24 540304113538 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.83528321 Sep 18 06:41:11 AM UTC 24 Sep 18 06:45:25 AM UTC 24 351665650822 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.4254302070 Sep 18 06:45:25 AM UTC 24 Sep 18 06:45:27 AM UTC 24 353814445 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1426929326 Sep 18 06:37:35 AM UTC 24 Sep 18 06:45:33 AM UTC 24 491104825579 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.2419934208 Sep 18 06:45:28 AM UTC 24 Sep 18 06:45:34 AM UTC 24 6020923324 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.2065382739 Sep 18 06:32:37 AM UTC 24 Sep 18 06:45:42 AM UTC 24 328811690915 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3494666684 Sep 18 06:44:59 AM UTC 24 Sep 18 06:45:49 AM UTC 24 18244816951 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.4128161528 Sep 18 06:43:41 AM UTC 24 Sep 18 06:46:04 AM UTC 24 330457337280 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1617053023 Sep 18 06:36:31 AM UTC 24 Sep 18 06:46:07 AM UTC 24 200537895099 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.669030814 Sep 18 06:44:58 AM UTC 24 Sep 18 06:46:07 AM UTC 24 43393989394 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.3113353911 Sep 18 06:37:53 AM UTC 24 Sep 18 06:46:11 AM UTC 24 355290942493 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.3586584313 Sep 18 06:46:14 AM UTC 24 Sep 18 06:46:27 AM UTC 24 5029497239 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.4114492617 Sep 18 06:36:34 AM UTC 24 Sep 18 06:46:28 AM UTC 24 187631479697 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2065624046 Sep 18 06:32:43 AM UTC 24 Sep 18 06:46:42 AM UTC 24 612985905687 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.595187627 Sep 18 06:46:42 AM UTC 24 Sep 18 06:46:49 AM UTC 24 1295282763 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.2118321654 Sep 18 06:41:06 AM UTC 24 Sep 18 06:46:51 AM UTC 24 509490613166 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.2409591856 Sep 18 06:46:51 AM UTC 24 Sep 18 06:46:55 AM UTC 24 491784884 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.1708343308 Sep 18 06:32:28 AM UTC 24 Sep 18 06:47:08 AM UTC 24 485834504906 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.1306225778 Sep 18 06:46:55 AM UTC 24 Sep 18 06:47:23 AM UTC 24 5734805964 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.2835114352 Sep 18 06:35:11 AM UTC 24 Sep 18 06:47:33 AM UTC 24 323680599262 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.1315279984 Sep 18 06:42:09 AM UTC 24 Sep 18 06:47:46 AM UTC 24 484127132013 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.3610836930 Sep 18 06:46:28 AM UTC 24 Sep 18 06:47:51 AM UTC 24 21759921325 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1467438668 Sep 18 06:39:36 AM UTC 24 Sep 18 06:47:56 AM UTC 24 614672889888 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.754732457 Sep 18 06:38:25 AM UTC 24 Sep 18 06:48:10 AM UTC 24 141150594631 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.4103464115 Sep 18 06:35:30 AM UTC 24 Sep 18 06:48:52 AM UTC 24 344698765242 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.598013069 Sep 18 06:45:20 AM UTC 24 Sep 18 06:48:59 AM UTC 24 204688595061 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.2935416204 Sep 18 06:32:30 AM UTC 24 Sep 18 06:49:12 AM UTC 24 461913822703 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.4124353665 Sep 18 06:48:59 AM UTC 24 Sep 18 06:49:21 AM UTC 24 4675845933 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.3568101111 Sep 18 06:42:41 AM UTC 24 Sep 18 06:49:25 AM UTC 24 165993964150 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.907783932 Sep 18 06:44:15 AM UTC 24 Sep 18 06:49:32 AM UTC 24 539805266082 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.3651922208 Sep 18 06:39:16 AM UTC 24 Sep 18 06:49:34 AM UTC 24 483828850859 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.1496083601 Sep 18 06:49:35 AM UTC 24 Sep 18 06:49:38 AM UTC 24 285111005 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.285163477 Sep 18 06:35:32 AM UTC 24 Sep 18 06:49:41 AM UTC 24 346748075946 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.1471953496 Sep 18 06:49:33 AM UTC 24 Sep 18 06:49:46 AM UTC 24 6853287042 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.3614119428 Sep 18 06:49:14 AM UTC 24 Sep 18 06:49:49 AM UTC 24 31356664840 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.866502185 Sep 18 06:47:52 AM UTC 24 Sep 18 06:49:49 AM UTC 24 207903072200 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.2814698486 Sep 18 06:56:23 AM UTC 24 Sep 18 06:56:25 AM UTC 24 400363670 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.1772667462 Sep 18 06:49:39 AM UTC 24 Sep 18 06:49:52 AM UTC 24 5922056331 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.141845327 Sep 18 06:41:28 AM UTC 24 Sep 18 06:49:52 AM UTC 24 93655995322 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.3423694 Sep 18 06:32:20 AM UTC 24 Sep 18 06:50:04 AM UTC 24 355250592162 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4090949108 Sep 18 06:49:26 AM UTC 24 Sep 18 06:50:12 AM UTC 24 79350756540 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3348821788 Sep 18 06:33:44 AM UTC 24 Sep 18 06:50:16 AM UTC 24 330691671825 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.574413248 Sep 18 06:43:53 AM UTC 24 Sep 18 06:50:20 AM UTC 24 330993129806 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.2247182071 Sep 18 06:35:55 AM UTC 24 Sep 18 06:50:29 AM UTC 24 99811668661 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1877786352 Sep 18 06:43:54 AM UTC 24 Sep 18 06:50:30 AM UTC 24 163443504395 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.1079381822 Sep 18 06:46:50 AM UTC 24 Sep 18 06:50:35 AM UTC 24 346250628674 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.3799822653 Sep 18 06:37:19 AM UTC 24 Sep 18 06:50:39 AM UTC 24 494441571926 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.3418234027 Sep 18 06:50:16 AM UTC 24 Sep 18 06:50:41 AM UTC 24 4994033264 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.54230979 Sep 18 06:50:40 AM UTC 24 Sep 18 06:50:43 AM UTC 24 388451266 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.4238680581 Sep 18 06:50:31 AM UTC 24 Sep 18 06:50:43 AM UTC 24 37631471829 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2624802737 Sep 18 06:46:08 AM UTC 24 Sep 18 06:50:49 AM UTC 24 402139871265 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.273933641 Sep 18 06:34:09 AM UTC 24 Sep 18 06:50:54 AM UTC 24 513947164929 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.611023069 Sep 18 06:48:53 AM UTC 24 Sep 18 06:50:55 AM UTC 24 184562518567 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.3335567487 Sep 18 06:50:41 AM UTC 24 Sep 18 06:50:55 AM UTC 24 5919554273 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.2622548252 Sep 18 06:42:31 AM UTC 24 Sep 18 06:50:57 AM UTC 24 514148252627 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.1192096964 Sep 18 06:50:21 AM UTC 24 Sep 18 06:51:09 AM UTC 24 35910353093 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1377660586 Sep 18 06:32:27 AM UTC 24 Sep 18 06:51:19 AM UTC 24 404944553805 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.3744073577 Sep 18 06:43:18 AM UTC 24 Sep 18 06:51:21 AM UTC 24 100252992721 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.1136760564 Sep 18 06:43:49 AM UTC 24 Sep 18 06:51:27 AM UTC 24 167529979437 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2134928271 Sep 18 06:41:06 AM UTC 24 Sep 18 06:51:27 AM UTC 24 201600987284 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.610650438 Sep 18 06:46:12 AM UTC 24 Sep 18 06:51:35 AM UTC 24 163787900100 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.1167164742 Sep 18 06:51:19 AM UTC 24 Sep 18 06:51:40 AM UTC 24 4610584777 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.597814097 Sep 18 06:51:41 AM UTC 24 Sep 18 06:51:43 AM UTC 24 489882319 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.1197597392 Sep 18 06:43:30 AM UTC 24 Sep 18 06:51:47 AM UTC 24 716132380409 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.895469812 Sep 18 06:51:28 AM UTC 24 Sep 18 06:51:52 AM UTC 24 5113902126 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.811062230 Sep 18 06:47:09 AM UTC 24 Sep 18 06:51:53 AM UTC 24 490507208829 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.1924733679 Sep 18 06:51:44 AM UTC 24 Sep 18 06:51:58 AM UTC 24 5796341025 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.1789443987 Sep 18 06:46:06 AM UTC 24 Sep 18 06:52:06 AM UTC 24 197734719284 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.999343789 Sep 18 06:51:23 AM UTC 24 Sep 18 06:52:19 AM UTC 24 26403203073 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2325871910 Sep 18 06:32:21 AM UTC 24 Sep 18 06:52:28 AM UTC 24 414145279133 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.2768043456 Sep 18 06:47:24 AM UTC 24 Sep 18 06:52:30 AM UTC 24 484646611602 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.1221284089 Sep 18 06:48:11 AM UTC 24 Sep 18 06:52:37 AM UTC 24 359848300048 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.1259129942 Sep 18 06:50:13 AM UTC 24 Sep 18 06:52:40 AM UTC 24 329130094563 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.2234294555 Sep 18 06:39:37 AM UTC 24 Sep 18 06:52:41 AM UTC 24 335250470855 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.4130871597 Sep 18 06:52:39 AM UTC 24 Sep 18 06:52:48 AM UTC 24 2878605391 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.596627407 Sep 18 06:49:50 AM UTC 24 Sep 18 06:52:56 AM UTC 24 160564572058 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.3800551617 Sep 18 06:52:42 AM UTC 24 Sep 18 06:53:02 AM UTC 24 26762930185 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3905178513 Sep 18 06:52:49 AM UTC 24 Sep 18 06:53:04 AM UTC 24 5859057198 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.1585925092 Sep 18 06:53:03 AM UTC 24 Sep 18 06:53:06 AM UTC 24 353092057 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.3589226692 Sep 18 06:53:04 AM UTC 24 Sep 18 06:53:11 AM UTC 24 6192399246 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.2101781502 Sep 18 06:44:55 AM UTC 24 Sep 18 06:53:16 AM UTC 24 531255263666 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.1884166433 Sep 18 06:46:28 AM UTC 24 Sep 18 06:53:28 AM UTC 24 85131118635 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.568340145 Sep 18 06:41:06 AM UTC 24 Sep 18 06:53:32 AM UTC 24 515727946704 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.1974134626 Sep 18 06:47:34 AM UTC 24 Sep 18 06:53:40 AM UTC 24 159245600225 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1197304933 Sep 18 06:44:19 AM UTC 24 Sep 18 06:54:00 AM UTC 24 204297990618 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3266422544 Sep 18 06:46:09 AM UTC 24 Sep 18 06:54:11 AM UTC 24 349116437583 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1576226642 Sep 18 06:50:56 AM UTC 24 Sep 18 06:54:26 AM UTC 24 611458266482 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.3940044172 Sep 18 06:54:27 AM UTC 24 Sep 18 06:54:49 AM UTC 24 5160001556 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.697108779 Sep 18 06:51:48 AM UTC 24 Sep 18 06:54:54 AM UTC 24 328130752862 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.4056717517 Sep 18 06:53:16 AM UTC 24 Sep 18 06:54:58 AM UTC 24 493239678989 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.3429069797 Sep 18 06:40:48 AM UTC 24 Sep 18 06:55:15 AM UTC 24 328068998166 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3067940306 Sep 18 06:50:55 AM UTC 24 Sep 18 06:55:20 AM UTC 24 490184136907 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.2346554504 Sep 18 06:39:13 AM UTC 24 Sep 18 06:55:22 AM UTC 24 325979780778 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.4098799309 Sep 18 06:55:21 AM UTC 24 Sep 18 06:55:23 AM UTC 24 582850414 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1885271054 Sep 18 06:54:59 AM UTC 24 Sep 18 06:55:26 AM UTC 24 3960193510 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2474983835 Sep 18 06:53:28 AM UTC 24 Sep 18 06:55:29 AM UTC 24 160150674963 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.4222302045 Sep 18 06:55:22 AM UTC 24 Sep 18 06:55:30 AM UTC 24 6094647469 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1695051984 Sep 18 06:45:49 AM UTC 24 Sep 18 06:55:37 AM UTC 24 332786975366 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.3577427829 Sep 18 06:40:39 AM UTC 24 Sep 18 06:55:48 AM UTC 24 336200219580 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.3021212881 Sep 18 06:50:49 AM UTC 24 Sep 18 06:55:50 AM UTC 24 494794959123 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.2139943920 Sep 18 06:41:58 AM UTC 24 Sep 18 06:55:52 AM UTC 24 327094500115 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.3852455202 Sep 18 06:37:41 AM UTC 24 Sep 18 06:55:57 AM UTC 24 650523299817 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.3495157488 Sep 18 06:55:58 AM UTC 24 Sep 18 06:56:02 AM UTC 24 3643360293 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2896739601 Sep 18 06:37:50 AM UTC 24 Sep 18 06:56:07 AM UTC 24 403468168050 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.3179155780 Sep 18 06:40:23 AM UTC 24 Sep 18 06:56:11 AM UTC 24 117908036901 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.696954738 Sep 18 06:35:12 AM UTC 24 Sep 18 06:56:19 AM UTC 24 489586831579 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.3358891608 Sep 18 06:37:05 AM UTC 24 Sep 18 06:56:22 AM UTC 24 495528597535 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.1520069374 Sep 18 06:56:03 AM UTC 24 Sep 18 06:56:27 AM UTC 24 26370885227 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2747280411 Sep 18 06:34:05 AM UTC 24 Sep 18 06:56:31 AM UTC 24 593744130687 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.767897862 Sep 18 06:49:46 AM UTC 24 Sep 18 06:56:32 AM UTC 24 328659912238 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2167247638 Sep 18 06:56:12 AM UTC 24 Sep 18 06:56:36 AM UTC 24 95813824015 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1616965523 Sep 18 06:42:10 AM UTC 24 Sep 18 06:56:42 AM UTC 24 324405157704 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.3603922432 Sep 18 06:53:07 AM UTC 24 Sep 18 06:56:45 AM UTC 24 161918723223 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.2655108102 Sep 18 06:54:50 AM UTC 24 Sep 18 06:56:49 AM UTC 24 38145841628 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.1183377802 Sep 18 06:56:26 AM UTC 24 Sep 18 06:56:53 AM UTC 24 5965663844 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.3451694029 Sep 18 06:55:27 AM UTC 24 Sep 18 06:57:09 AM UTC 24 166204684221 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.1608198226 Sep 18 06:57:10 AM UTC 24 Sep 18 06:57:13 AM UTC 24 4580201520 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup_fixed.356372810 Sep 18 06:56:46 AM UTC 24 Sep 18 06:57:21 AM UTC 24 205855084972 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.3663133205 Sep 18 06:32:20 AM UTC 24 Sep 18 06:57:22 AM UTC 24 497009975173 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.1049043968 Sep 18 06:55:29 AM UTC 24 Sep 18 06:57:29 AM UTC 24 329727625483 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.2090149175 Sep 18 06:51:54 AM UTC 24 Sep 18 06:57:53 AM UTC 24 488444705598 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.372666501 Sep 18 06:56:42 AM UTC 24 Sep 18 06:57:55 AM UTC 24 180355258125 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.2354948366 Sep 18 06:57:53 AM UTC 24 Sep 18 06:57:57 AM UTC 24 478904930 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.1690941308 Sep 18 06:53:11 AM UTC 24 Sep 18 06:58:00 AM UTC 24 168073655337 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.984003340 Sep 18 06:57:56 AM UTC 24 Sep 18 06:58:02 AM UTC 24 6010500743 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.3711080925 Sep 18 06:49:42 AM UTC 24 Sep 18 06:58:03 AM UTC 24 165308813635 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_17/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3558712695 Sep 18 06:57:23 AM UTC 24 Sep 18 06:58:04 AM UTC 24 39591961127 ps