Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23145

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19914

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3231

1

T9

6

T12

4

T17

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17259

1

T2

20

T3

20

T4

19

auto[1]

5886

1

T5

5

T8

6

T11

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19319

1

T2

20

T3

20

T4

19

auto[1]

3826

1

T8

1

T9

3

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T217	1		-	-		-	-
values[0]	40	1			T224	14		T225	2		T226	24
values[1]	542	1			T8	6		T152	1		T142	1
values[2]	794	1			T45	1		T85	1		T56	10
values[3]	619	1			T182	10		T227	25		T164	23
values[4]	2654	1			T9	6		T13	5		T14	1
values[5]	565	1			T5	5		T16	4		T139	7
values[6]	635	1			T139	3		T143	18		T144	27
values[7]	830	1			T11	1		T46	3		T35	2
values[8]	733	1			T153	11		T228	29		T137	4
values[9]	1188	1			T12	4		T44	2		T17	24
minimum	14544	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	768	1			T8	6		T45	1		T85	1
values[1]	704	1			T56	10		T39	2		T144	28
values[2]	703	1			T52	4		T140	7		T148	1
values[3]	2652	1			T5	5		T9	6		T13	5
values[4]	613	1			T16	4		T139	7		T153	9
values[5]	640	1			T46	3		T139	3		T151	12
values[6]	782	1			T35	2		T144	27		T137	4
values[7]	696	1			T11	1		T44	2		T17	9
values[8]	893	1			T12	4		T17	15		T153	14
values[9]	150	1			T141	10		T32	16		T147	1
minimum	14544	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

3926

1

T5

4

T8

1

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T8	5		T152	1		T140	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T45	1		T85	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T229	1		T146	4		T230	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T56	10		T39	2		T144	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T52	4		T140	4		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T182	1		T227	7		T164	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T5	5		T13	1		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	4		T35	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T16	3		T153	9		T143	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T139	7		T196	1		T231	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T139	3		T151	1		T232	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T46	1		T227	12		T171	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T35	1		T137	3		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T35	1		T144	13		T145	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T11	1		T44	2		T139	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T17	3		T163	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T153	14		T148	1		T233	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T12	3		T17	5		T159	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T141	1		T155	18		T234	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T32	5		T147	1		T235	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T2	20		T3	20		T4	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T8	1		T140	14		T161	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T149	9		T236	2		T187	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T229	10		T146	4		T230	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T144	14		T160	11		T237	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T140	3		T187	4		T168	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T182	9		T227	18		T164	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T13	4		T141	10		T36	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	2		T228	6		T138	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T16	1		T143	11		T140	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T231	19		T238	2		T176	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T151	11		T232	20		T168	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T46	2		T227	9		T171	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T137	1		T41	5		T105	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T144	14		T145	12		T171	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T228	14		T233	19		T187	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T17	6		T145	4		T224	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T233	8		T164	13		T239	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	1		T17	10		T53	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T141	9		T155	18		T234	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T32	11		T240	12		T241	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T217	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T224	10		T226	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T225	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	5		T152	1		T140	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T142	1		T159	15		T236	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T229	1		T161	7		T146	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T45	1		T85	1		T56	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T187	6		T168	1		T237	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T182	1		T227	7		T164	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1442	1			T13	1		T14	1		T15	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T9	4		T35	1		T228	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	5		T16	3		T153	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T139	7		T142	1		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T139	3		T143	7		T232	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T144	13		T227	12		T171	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T11	1		T35	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T46	1		T35	1		T145	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T153	11		T228	15		T137	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T145	7		T224	20		T242	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T44	2		T141	1		T139	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T12	3		T17	8		T32	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T2	20		T3	20		T4	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T224	4		T226	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T225	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	1		T140	14		T236	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T236	2		T243	10		T244	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T229	10		T161	7		T146	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T144	14		T149	9		T160	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T187	4		T168	14		T237	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T182	9		T227	18		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T13	4		T141	10		T36	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T9	2		T228	6		T138	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T16	1		T140	1		T149	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T171	5		T231	19		T245	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T143	11		T232	20		T168	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T144	14		T227	9		T171	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T151	11		T41	5		T105	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T46	2		T145	12		T171	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T228	14		T137	1		T187	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T145	4		T224	11		T242	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T141	9		T233	27		T164	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	1		T17	16		T32	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T8	5		T152	1		T140	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T45	1		T85	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T229	11		T146	5		T230	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T56	1		T39	2		T144	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T52	2		T140	4		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T182	10		T227	19		T164	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T5	1		T13	5		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	4		T35	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T16	3		T153	1		T143	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T139	1		T196	1		T231	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T139	1		T151	12		T232	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T46	3		T227	10		T171	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T35	1		T137	3		T41	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T35	1		T144	15		T145	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	1		T44	2		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T17	7		T163	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T153	2		T148	1		T233	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	3		T17	11		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T141	10		T155	19		T234	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T32	12		T147	1		T235	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14544	1			T2	20		T3	20		T4	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	1		T140	13		T161	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T159	14		T236	11		T187	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T146	3		T230	12		T103	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T56	9		T144	13		T170	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T52	2		T140	3		T183	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T227	6		T164	12		T203	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T5	4		T15	9		T37	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	2		T228	6		T138	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T16	1		T153	8		T143	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T139	6		T231	19		T246	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T139	2		T73	2		T247	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T227	11		T171	4		T203	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T137	1		T105	11		T248	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T144	12		T145	10		T171	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T139	12		T228	14		T233	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T17	2		T145	6		T224	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T153	12		T233	9		T170	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	1		T17	4		T159	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T155	17		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T32	4		T235	13		T240	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T217	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T224	5		T226	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T225	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T8	5		T152	1		T140	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T142	1		T159	1		T236	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T229	11		T161	8		T146	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T45	1		T85	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T187	5		T168	15		T237	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T182	10		T227	19		T164	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T13	5		T14	1		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	4		T35	1		T228	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T16	3		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T139	1		T142	1		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T139	1		T143	12		T232	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T144	15		T227	10		T171	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	1		T35	1		T151	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T46	3		T35	1		T145	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T153	1		T228	15		T137	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T145	5		T224	12		T242	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T44	2		T141	10		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T12	3		T17	18		T32	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14544	1			T2	20		T3	20		T4	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T224	9		T226	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	1		T140	13		T236	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T159	14		T236	11		T243	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T161	6		T146	3		T169	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T56	9		T144	13		T170	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T187	5		T237	6		T230	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T227	6		T164	12		T203	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1110	1			T15	9		T37	14		T52	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T9	2		T228	6		T138	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	4		T16	1		T153	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T139	6		T171	9		T203	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T139	2		T143	6		T73	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T144	12		T227	11		T171	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T105	11		T247	4		T24	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T145	10		T171	8		T249	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T153	10		T228	14		T137	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T145	6		T224	19		T102	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T139	12		T153	2		T233	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T12	1		T17	6		T32	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

3926

1

T5

4

T8

1

T9

2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23145

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19671

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3474

1

T5

5

T8

6

T9

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17707

1

T2

20

T3

20

T4

19

auto[1]

5438

1

T8

6

T9

6

T13

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19319

1

T2

20

T3

20

T4

19

auto[1]

3826

1

T8

1

T9

3

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	34	1			T250	8		T251	13		T252	13
values[1]	748	1			T11	1		T141	10		T139	13
values[2]	577	1			T46	3		T85	1		T153	9
values[3]	661	1			T85	1		T35	1		T140	28
values[4]	746	1			T5	5		T8	6		T39	2
values[5]	2767	1			T13	5		T14	1		T15	10
values[6]	623	1			T56	10		T152	1		T141	11
values[7]	562	1			T12	4		T16	4		T17	9
values[8]	635	1			T44	2		T32	16		T140	7
values[9]	1248	1			T9	6		T17	15		T45	1
minimum	14544	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	848	1			T11	1		T85	1		T141	10
values[1]	689	1			T46	3		T85	1		T153	9
values[2]	584	1			T35	1		T39	2		T148	1
values[3]	2846	1			T5	5		T8	6		T13	5
values[4]	678	1			T35	1		T139	10		T196	1
values[5]	657	1			T56	10		T152	1		T145	23
values[6]	497	1			T12	4		T16	4		T17	9
values[7]	785	1			T44	2		T32	16		T151	12
values[8]	710	1			T9	6		T17	15		T45	1
values[9]	293	1			T183	10		T253	24		T203	22
minimum	14558	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

3926

1

T5

4

T8

1

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	1		T85	1		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T236	14		T187	20		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T85	1		T153	9		T140	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T46	1		T149	1		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	2		T148	1		T228	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T35	1		T53	4		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T13	1		T14	1		T15	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T5	5		T8	5		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T139	7		T233	10		T146	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T35	1		T139	3		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T56	10		T227	7		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T152	1		T145	11		T138	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	3		T17	3		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T16	3		T105	15		T239	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T32	5		T245	10		T254	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T44	2		T151	1		T161	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T17	5		T153	11		T140	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	4		T45	1		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T203	22		T155	16		T42	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T183	10		T253	13		T255	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T236	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T141	9		T144	14		T41	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T236	14		T187	14		T168	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T140	14		T54	2		T224	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T46	2		T149	9		T160	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T228	6		T145	4		T242	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T53	2		T182	9		T165	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T13	4		T36	10		T201	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	1		T229	10		T171	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T233	8		T146	4		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T143	11		T144	14		T228	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T227	18		T256	6		T171	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T145	12		T138	1		T187	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	1		T17	6		T141	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T16	1		T105	13		T239	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T32	11		T245	9		T254	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T151	11		T161	7		T227	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T17	10		T140	3		T230	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	2		T232	4		T164	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T155	14		T99	13		T238	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T253	11		T255	9		T257	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T236	2		-	-		-	-