Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23145

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19665

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3480

1

T5

5

T9

6

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17718

1

T2

20

T3

20

T4

19

auto[1]

5427

1

T8

6

T9

6

T44

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19319

1

T2

20

T3

20

T4

19

auto[1]

3826

1

T8

1

T9

3

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T163	1		T258	4		T272	1
values[0]	104	1			T196	1		T262	19		T290	22
values[1]	704	1			T35	1		T153	9		T154	13
values[2]	563	1			T153	11		T142	1		T144	28
values[3]	736	1			T16	4		T17	9		T45	1
values[4]	750	1			T85	1		T32	16		T144	27
values[5]	2798	1			T12	4		T13	5		T14	1
values[6]	692	1			T5	5		T9	6		T56	10
values[7]	635	1			T44	2		T17	15		T152	1
values[8]	624	1			T11	1		T139	7		T140	9
values[9]	981	1			T8	6		T141	11		T39	2
minimum	14544	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	852	1			T35	1		T153	20		T196	1
values[1]	667	1			T85	1		T142	1		T236	28
values[2]	742	1			T16	4		T17	9		T45	1
values[3]	2880	1			T12	4		T13	5		T14	1
values[4]	646	1			T5	5		T9	6		T52	4
values[5]	648	1			T44	2		T17	15		T56	10
values[6]	637	1			T35	1		T139	7		T142	1
values[7]	653	1			T11	1		T141	11		T140	7
values[8]	697	1			T8	6		T39	2		T140	28
values[9]	143	1			T159	13		T160	12		T256	17
minimum	14580	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

3926

1

T5

4

T8

1

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T153	20		T196	1		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T35	1		T144	14		T159	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T236	14		T237	7		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T85	1		T142	1		T187	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T45	1		T46	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T16	3		T17	3		T139	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1487	1			T12	3		T13	1		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T85	1		T35	1		T233	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T52	4		T242	1		T231	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	5		T9	4		T228	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T44	2		T56	10		T227	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T17	5		T152	1		T228	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T35	1		T140	1		T145	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T139	7		T142	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T140	4		T137	3		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	1		T141	1		T138	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	5		T39	2		T140	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T148	2		T53	4		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T159	13		T100	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T160	1		T256	11		T204	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14452	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T304	1		T305	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T154	12		T229	10		T227	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T144	14		T164	13		T173	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T236	14		T237	2		T165	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T187	14		T171	12		T269	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T46	2		T141	9		T143	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T16	1		T17	6		T227	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T12	1		T13	4		T32	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T233	19		T151	11		T232	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T242	5		T231	9		T158	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	2		T228	14		T187	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T227	9		T232	16		T105	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T17	10		T228	6		T149	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T140	1		T145	12		T168	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T145	4		T168	14		T260	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T140	3		T137	1		T230	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T141	10		T138	1		T248	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	1		T140	14		T161	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T53	2		T149	6		T187	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T100	14		T306	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T160	11		T256	6		T165	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T9	1		T21	4		T39	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T304	1		T305	15		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T163	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T258	3		T272	1		T165	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T196	1		T262	5		T290	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T304	1		T307	9		T308	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T153	9		T154	1		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T35	1		T164	13		T269	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T153	11		T181	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T142	1		T144	14		T159	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T45	1		T46	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T16	3		T17	3		T85	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T32	5		T144	13		T54	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T85	1		T233	15		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1447	1			T12	3		T13	1		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T146	4		T232	1		T187	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T56	10		T227	12		T105	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	5		T9	4		T228	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T44	2		T35	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T17	5		T152	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T140	5		T137	3		T145	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	1		T139	7		T148	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	5		T39	2		T140	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T141	1		T148	1		T53	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T258	1		T165	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T262	14		T290	10		T226	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T304	1		T307	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T154	12		T229	10		T227	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T164	13		T269	15		T155	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T102	5		T165	5		T99	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T144	14		T171	12		T99	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T46	2		T141	9		T143	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T16	1		T17	6		T227	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T32	11		T144	14		T54	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T233	19		T151	11		T254	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T12	1		T13	4		T36	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T232	4		T187	4		T41	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T227	9		T105	13		T245	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	2		T228	20		T149	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T232	16		T168	2		T253	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T17	10		T138	1		T237	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T140	4		T137	1		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T145	4		T168	14		T248	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T8	1		T140	14		T161	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T141	10		T53	2		T149	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T153	2		T196	1		T154	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T35	1		T144	15		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T236	15		T237	3		T165	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T85	1		T142	1		T187	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T45	1		T46	3		T141	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T16	3		T17	7		T139	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T12	3		T13	5		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T85	1		T35	1		T233	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T52	2		T242	6		T231	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	1		T9	4		T228	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T44	2		T56	1		T227	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T17	11		T152	1		T228	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T35	1		T140	2		T145	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T139	1		T142	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T140	4		T137	3		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	1		T141	11		T138	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	5		T39	2		T140	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T148	2		T53	6		T149	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T159	1		T100	15		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T160	12		T256	7		T204	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14546	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T304	2		T305	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T153	18		T183	9		T227	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T144	13		T159	14		T164	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T236	13		T237	6		T283	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T187	19		T171	17		T269	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T143	6		T144	12		T54	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T16	1		T17	2		T139	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1152	1			T12	1		T15	9		T32	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T233	14		T203	21		T248	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T52	2		T231	11		T309	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	4		T9	2		T228	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T56	9		T227	11		T105	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	4		T228	6		T146	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T145	10		T253	12		T203	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T139	6		T170	14		T145	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T140	3		T137	1		T230	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T138	1		T248	13		T243	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	1		T140	13		T161	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T170	15		T258	1		T243	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T159	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T256	10		T310	7		T311	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T177	16		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T163	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T258	3		T272	1		T165	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T196	1		T262	15		T290	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T304	2		T307	8		T308	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T153	1		T154	13		T229	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T35	1		T164	14		T269	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T153	1		T181	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T142	1		T144	15		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T45	1		T46	3		T141	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	3		T17	7		T85	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T32	12		T144	15		T54	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T85	1		T233	20		T151	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T12	3		T13	5		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T146	1		T232	5		T187	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T56	1		T227	10		T105	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	1		T9	4		T228	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T44	2		T35	1		T232	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T17	11		T152	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T140	6		T137	3		T145	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	1		T139	1		T148	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	5		T39	2		T140	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T141	11		T148	1		T53	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14544	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T258	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T262	4		T290	11		T226	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T307	8		T308	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T153	8		T183	9		T227	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T164	12		T269	15		T155	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T153	10		T102	8		T283	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T144	13		T159	14		T171	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T143	6		T236	13		T164	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T16	1		T17	2		T139	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T32	4		T144	12		T54	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T233	14		T203	21		T254	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1107	1			T12	1		T15	9		T37	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T146	3		T187	5		T102	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T56	9		T227	11		T105	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	4		T9	2		T228	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T253	12		T203	11		T102	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T17	4		T170	14		T138	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T140	3		T137	1		T145	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T139	6		T170	15		T145	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	1		T140	13		T159	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T256	10		T243	13		T247	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

3926

1

T5

4

T8

1

T9

2