Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23145

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19636

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3509

1

T5

5

T9

6

T12

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17340

1

T2

20

T3

20

T4

19

auto[1]

5805

1

T12

4

T13

5

T14

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19319

1

T2

20

T3

20

T4

19

auto[1]

3826

1

T8

1

T9

3

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	231	1			T52	4		T144	28		T243	11
values[0]	12	1			T272	1		T280	11		-	-
values[1]	764	1			T16	4		T46	3		T56	10
values[2]	2546	1			T5	5		T13	5		T14	1
values[3]	710	1			T141	10		T35	1		T154	13
values[4]	632	1			T8	6		T9	6		T11	1
values[5]	563	1			T39	2		T139	13		T153	9
values[6]	652	1			T17	15		T85	1		T152	1
values[7]	546	1			T12	4		T85	1		T32	16
values[8]	793	1			T17	9		T141	11		T153	3
values[9]	1152	1			T45	1		T139	7		T148	1
minimum	14544	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	739	1			T5	5		T16	4		T46	3
values[1]	2743	1			T13	5		T14	1		T15	10
values[2]	554	1			T141	10		T35	1		T154	13
values[3]	559	1			T8	6		T9	6		T11	1
values[4]	673	1			T17	15		T39	2		T196	1
values[5]	549	1			T12	4		T85	1		T152	1
values[6]	645	1			T85	1		T141	11		T32	16
values[7]	834	1			T17	9		T45	1		T153	3
values[8]	982	1			T139	7		T52	4		T140	7
values[9]	132	1			T169	11		T272	1		T105	28
minimum	14735	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

3926

1

T5

4

T8

1

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T16	3		T46	1		T232	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	5		T56	10		T153	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T13	1		T14	1		T15	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T35	1		T148	1		T228	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T154	1		T137	3		T103	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T141	1		T35	1		T181	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	5		T11	1		T44	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	4		T139	13		T153	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T17	5		T143	7		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T39	2		T196	1		T144	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T140	1		T160	1		T236	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	3		T85	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T85	1		T161	7		T145	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T141	1		T32	5		T140	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T45	1		T153	3		T53	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T17	3		T170	16		T22	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T139	7		T140	4		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T52	4		T233	15		T146	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T272	1		T42	3		T312	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T169	11		T105	15		T275	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14489	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T23	2		T273	9		T174	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T16	1		T46	2		T232	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T237	2		T41	12		T155	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T13	4		T36	10		T201	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T228	6		T256	6		T253	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T154	12		T137	1		T103	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T141	9		T248	4		T173	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T8	1		T145	12		T258	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	2		T233	8		T160	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T17	10		T143	11		T182	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T144	14		T228	14		T227	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T140	1		T236	14		T239	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	1		T151	11		T224	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T161	7		T145	4		T187	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T141	10		T32	11		T140	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T53	2		T149	6		T54	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T17	6		T168	14		T237	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T140	3		T144	14		T149	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T233	19		T146	4		T164	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T277	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T105	13		T278	11		T279	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	1		T21	4		T39	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T282	15		T313	12		T314	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T144	14		T259	6		T315	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T52	4		T243	3		T247	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T280	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T272	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T16	3		T46	1		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T56	10		T153	11		T237	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T13	1		T14	1		T15	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	5		T35	1		T228	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T154	1		T236	12		T146	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T141	1		T35	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	5		T11	1		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	4		T233	10		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T187	20		T258	3		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T39	2		T139	13		T153	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T17	5		T143	7		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T85	1		T152	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T85	1		T161	7		T145	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T12	3		T32	5		T159	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T153	3		T140	4		T53	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T17	3		T141	1		T140	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T45	1		T139	7		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T233	15		T146	4		T164	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T144	14		T259	8		T315	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T243	8		T247	10		T290	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T280	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T16	1		T46	2		T232	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T237	2		T155	14		T282	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	900	1			T13	4		T36	10		T201	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T228	6		T256	6		T41	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T154	12		T236	2		T230	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T141	9		T248	4		T173	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T8	1		T137	1		T145	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T9	2		T233	8		T160	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T187	14		T258	1		T276	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T144	14		T228	14		T227	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T17	10		T143	11		T140	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T151	11		T164	10		T224	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T161	7		T145	4		T41	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T12	1		T32	11		T229	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T140	3		T53	2		T149	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T17	6		T141	10		T140	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T149	9		T227	18		T168	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T233	19		T146	4		T164	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T16	3		T46	3		T232	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	1		T56	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T13	5		T14	1		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T35	1		T148	1		T228	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T154	13		T137	3		T103	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T141	10		T35	1		T181	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T8	5		T11	1		T44	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T9	4		T139	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T17	11		T143	12		T182	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T39	2		T196	1		T144	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T140	2		T160	1		T236	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	3		T85	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T85	1		T161	8		T145	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T141	11		T32	12		T140	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T45	1		T153	1		T53	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T17	7		T170	1		T22	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T139	1		T140	4		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T52	2		T233	20		T146	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T272	1		T42	1		T312	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T169	1		T105	14		T275	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14587	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T23	2		T273	1		T174	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T16	1		T203	21		T172	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	4		T56	9		T153	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1056	1			T15	9		T37	14		T139	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T228	6		T183	9		T256	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T137	1		T103	9		T90	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T248	5		T173	9		T316	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T8	1		T145	10		T203	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	2		T139	12		T153	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T17	4		T143	6		T187	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T144	12		T228	14		T227	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T236	13		T261	23		T176	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	1		T224	9		T249	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T161	6		T145	6		T224	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T32	4		T140	13		T159	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T153	2		T54	1		T145	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T17	2		T170	15		T237	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T139	6		T140	3		T144	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T52	2		T233	14		T146	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T42	2		T277	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T169	10		T105	14		T275	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T273	15		T251	5		T317	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T273	8		T282	14		T314	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T144	15		T259	9		T315	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T52	2		T243	9		T247	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T280	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T272	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T16	3		T46	3		T232	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T56	1		T153	1		T237	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T13	5		T14	1		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	1		T35	1		T228	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T154	13		T236	3		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T141	10		T35	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T8	5		T11	1		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T9	4		T233	9		T160	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T187	15		T258	3		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T39	2		T139	1		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T17	11		T143	12		T140	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T85	1		T152	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T85	1		T161	8		T145	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	3		T32	12		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T153	1		T140	4		T53	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T17	7		T141	11		T140	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T45	1		T139	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T233	20		T146	5		T164	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14544	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T144	13		T259	5		T315	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T52	2		T243	2		T247	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T280	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T16	1		T203	21		T172	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T56	9		T153	10		T237	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T15	9		T37	14		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	4		T228	6		T183	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T236	11		T146	3		T230	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T248	5		T173	9		T259	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T8	1		T137	1		T145	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	2		T233	9		T227	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T187	19		T258	1		T276	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T139	12		T153	8		T144	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T17	4		T143	6		T236	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T164	12		T224	9		T231	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T161	6		T145	6		T224	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T12	1		T32	4		T159	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T153	2		T140	3		T54	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T17	2		T140	13		T170	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T139	6		T170	14		T227	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T233	14		T146	3		T164	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

3926

1

T5

4

T8

1

T9

2