Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23145

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19478

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3667

1

T9

6

T11

1

T44

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17338

1

T2

20

T3

20

T4

19

auto[1]

5807

1

T8

1

T9

6

T11

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19319

1

T2

20

T3

20

T4

19

auto[1]

3826

1

T8

1

T9

3

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	331	1			T8	1		T12	6		T16	1
values[0]	54	1			T93	1		T315	16		T270	12
values[1]	608	1			T141	11		T32	16		T228	29
values[2]	2520	1			T13	5		T14	1		T15	10
values[3]	620	1			T46	3		T152	1		T139	10
values[4]	735	1			T9	6		T85	1		T153	9
values[5]	673	1			T8	6		T85	1		T141	10
values[6]	652	1			T17	9		T149	7		T236	28
values[7]	637	1			T44	2		T16	4		T45	1
values[8]	672	1			T12	4		T17	15		T35	2
values[9]	1385	1			T5	5		T11	1		T56	10
minimum	14258	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	749	1			T141	11		T32	16		T228	29
values[1]	2583	1			T13	5		T14	1		T15	10
values[2]	713	1			T46	3		T139	10		T153	9
values[3]	598	1			T8	6		T85	1		T196	1
values[4]	668	1			T9	6		T85	1		T141	10
values[5]	614	1			T17	9		T140	28		T144	27
values[6]	776	1			T44	2		T16	4		T45	1
values[7]	728	1			T12	4		T17	15		T35	2
values[8]	899	1			T5	5		T11	1		T142	1
values[9]	250	1			T56	10		T148	1		T233	34
minimum	14567	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

3926

1

T5

4

T8

1

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T141	1		T32	5		T228	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T168	1		T318	3		T291	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T13	1		T14	1		T15	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T35	1		T164	13		T187	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T46	1		T139	3		T153	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T139	7		T171	10		T242	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T8	5		T85	1		T140	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T196	1		T159	13		T227	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T85	1		T39	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T9	4		T141	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T17	3		T144	13		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T140	14		T236	14		T138	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T16	3		T45	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T44	2		T229	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	3		T35	1		T139	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T17	5		T35	1		T153	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T5	5		T142	1		T137	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	1		T149	1		T54	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T148	1		T145	7		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T56	10		T233	15		T256	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14437	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T231	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T141	10		T32	11		T228	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T168	2		T268	10		T316	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	878	1			T13	4		T36	10		T201	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T164	13		T187	14		T105	39
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T46	2		T144	14		T242	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T171	5		T242	11		T269	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	1		T140	3		T253	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T227	18		T247	3		T255	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T154	12		T228	6		T243	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	2		T141	9		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T17	6		T144	14		T149	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T140	14		T236	14		T138	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T16	1		T250	22		T241	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T229	10		T160	11		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	1		T233	8		T182	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T17	10		T143	11		T236	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T137	1		T227	14		T258	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T149	9		T54	2		T146	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T145	4		T283	5		T234	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T233	19		T256	6		T73	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T231	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T8	1		T12	6		T16	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T237	14		T99	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T93	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T315	13		T270	12		T319	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T141	1		T32	5		T228	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T168	1		T231	12		T318	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T13	1		T14	1		T15	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T35	1		T203	22		T272	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T46	1		T152	1		T139	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T139	7		T164	13		T187	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T85	1		T153	9		T140	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	4		T196	1		T159	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T8	5		T85	1		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T141	1		T151	1		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T17	3		T149	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T236	14		T138	3		T187	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T16	3		T45	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T44	2		T140	14		T229	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	3		T35	1		T139	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T17	5		T35	1		T153	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T5	5		T142	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	416	1			T11	1		T56	10		T233	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14149	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T29	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T237	11		T99	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T315	3		T320	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T141	10		T32	11		T228	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T168	2		T231	9		T321	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	885	1			T13	4		T36	10		T201	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T105	17		T245	9		T268	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T46	2		T140	1		T144	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T164	13		T187	14		T171	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T140	3		T253	11		T269	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	2		T227	18		T242	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	1		T154	12		T228	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T141	9		T151	11		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T17	6		T149	6		T322	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T236	14		T138	1		T187	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T16	1		T144	14		T248	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T140	14		T229	10		T160	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	1		T233	8		T182	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T17	10		T143	11		T232	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T137	1		T145	4		T227	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T233	19		T149	9		T54	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T141	11		T32	12		T228	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T168	3		T318	3		T291	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T13	5		T14	1		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T35	1		T164	14		T187	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T46	3		T139	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T139	1		T171	6		T242	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	5		T85	1		T140	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T196	1		T159	1		T227	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T85	1		T39	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	4		T141	10		T151	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T17	7		T144	15		T149	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T140	15		T236	15		T138	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T16	3		T45	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T44	2		T229	11		T160	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	3		T35	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T17	11		T35	1		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T5	1		T142	1		T137	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T11	1		T149	10		T54	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T148	1		T145	5		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T56	1		T233	20		T256	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14545	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T231	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T32	4		T228	14		T161	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T291	12		T155	7		T296	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T15	9		T37	14		T170	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T164	12		T187	19		T203	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T139	2		T153	8		T144	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T139	6		T171	9		T269	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	1		T140	3		T170	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T159	12		T227	6		T247	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T159	14		T228	6		T169	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	2		T224	19		T273	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T17	2		T144	12		T248	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T140	13		T236	13		T138	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T16	1		T145	2		T177	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T145	10		T203	11		T224	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	1		T139	12		T153	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T17	4		T153	10		T143	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	4		T137	1		T227	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T54	1		T183	9		T146	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T145	6		T283	7		T251	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T56	9		T233	14		T256	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T24	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T231	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T8	1		T12	6		T16	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T237	12		T99	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T93	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T315	4		T270	1		T319	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T141	11		T32	12		T228	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T168	3		T231	10		T318	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T13	5		T14	1		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T35	1		T203	1		T272	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T46	3		T152	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T139	1		T164	14		T187	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T85	1		T153	1		T140	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	4		T196	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	5		T85	1		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T141	10		T151	12		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T17	7		T149	7		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T236	15		T138	3		T187	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T16	3		T45	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T44	2		T140	15		T229	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	3		T35	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T17	11		T35	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T5	1		T142	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	439	1			T11	1		T56	1		T233	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14258	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T29	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T237	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T315	12		T270	11		T320	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T32	4		T228	14		T227	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T231	11		T291	12		T155	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T15	9		T37	14		T161	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T203	21		T105	11		T245	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T139	2		T144	13		T164	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T139	6		T164	12		T187	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T153	8		T140	3		T159	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	2		T159	12		T227	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T8	1		T228	6		T102	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T224	19		T273	8		T157	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T17	2		T169	10		T235	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T236	13		T138	1		T187	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T16	1		T144	12		T145	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T140	13		T236	11		T145	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T12	1		T139	12		T153	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T17	4		T153	10		T143	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T5	4		T137	1		T145	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T56	9		T233	14		T54	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

3926

1

T5

4

T8

1

T9

2