Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23145

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19535

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3610

1

T8

6

T17

9

T45

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17602

1

T2

20

T3

20

T4

19

auto[1]

5543

1

T8

6

T13

5

T14

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19319

1

T2

20

T3

20

T4

19

auto[1]

3826

1

T8

1

T9

3

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	259	1			T17	15		T232	5		T253	24
values[0]	84	1			T187	34		T250	8		T251	13
values[1]	726	1			T11	1		T141	10		T139	13
values[2]	563	1			T46	3		T85	1		T153	9
values[3]	647	1			T85	1		T35	1		T228	13
values[4]	834	1			T5	5		T8	6		T39	2
values[5]	2660	1			T13	5		T14	1		T15	10
values[6]	635	1			T56	10		T152	1		T141	11
values[7]	536	1			T12	4		T16	4		T17	9
values[8]	648	1			T44	2		T32	16		T140	7
values[9]	1009	1			T9	6		T45	1		T35	1
minimum	14544	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	629	1			T11	1		T85	1		T141	10
values[1]	642	1			T46	3		T85	1		T153	9
values[2]	584	1			T35	1		T148	1		T228	13
values[3]	2877	1			T5	5		T8	6		T13	5
values[4]	632	1			T35	1		T139	10		T196	1
values[5]	677	1			T56	10		T152	1		T141	11
values[6]	464	1			T12	4		T16	4		T17	9
values[7]	737	1			T44	2		T32	16		T151	12
values[8]	828	1			T9	6		T17	15		T45	1
values[9]	246	1			T183	10		T253	24		T203	22
minimum	14829	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

3926

1

T5

4

T8

1

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	1		T85	1		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T236	14		T203	20		T169	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T85	1		T140	14		T181	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T46	1		T153	9		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T228	7		T145	7		T172	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T35	1		T148	1		T53	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T5	5		T13	1		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T8	5		T142	1		T52	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T148	1		T233	10		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T35	1		T139	10		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T56	10		T152	1		T227	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T141	1		T228	15		T145	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	3		T16	3		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T17	3		T105	15		T239	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T44	2		T32	5		T245	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T151	1		T145	3		T227	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	4		T17	5		T153	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T45	1		T35	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T291	13		T155	16		T42	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T183	10		T253	13		T203	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14498	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T187	20		T168	1		T238	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T141	9		T144	14		T54	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T236	14		T231	8		T250	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T140	14		T224	4		T243	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T46	2		T149	9		T160	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T228	6		T145	4		T242	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T53	2		T182	9		T165	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T13	4		T36	10		T201	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T8	1		T229	10		T171	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T233	8		T146	4		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T143	11		T144	14		T242	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T227	18		T187	1		T171	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T141	10		T228	14		T145	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	1		T16	1		T154	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T17	6		T105	13		T239	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T32	11		T245	9		T254	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T151	11		T227	14		T102	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	2		T17	10		T140	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T232	4		T164	13		T102	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T155	14		T99	13		T304	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T253	11		T238	1		T257	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	1		T21	4		T39	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T187	14		T168	2		T238	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T17	5		T291	13		T99	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T232	1		T253	13		T231	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T252	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T187	20		T250	1		T251	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T11	1		T141	1		T139	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T236	14		T168	1		T203	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T85	1		T140	14		T144	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T46	1		T153	9		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T85	1		T228	7		T181	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T35	1		T53	4		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	5		T39	2		T153	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T8	5		T52	4		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T13	1		T14	1		T15	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T35	1		T139	10		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T56	10		T152	1		T227	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T141	1		T196	1		T143	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	3		T16	3		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T17	3		T100	1		T156	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T44	2		T32	5		T140	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T151	1		T145	3		T227	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T9	4		T153	11		T230	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T45	1		T35	1		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T17	10		T99	13		T304	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T232	4		T253	11		T231	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T252	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T187	14		T250	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T141	9		T54	2		T236	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T236	14		T168	2		T231	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T140	14		T144	14		T224	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T46	2		T149	9		T160	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T228	6		T145	4		T242	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T53	2		T182	9		T165	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T233	19		T149	6		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T8	1		T229	10		T171	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	916	1			T13	4		T36	10		T201	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T105	17		T231	11		T173	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T227	18		T187	5		T171	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T141	10		T143	11		T144	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	1		T16	1		T154	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T17	6		T100	14		T156	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T32	11		T140	3		T161	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T151	11		T227	14		T102	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	2		T230	8		T41	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T164	13		T102	2		T244	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	1		T85	1		T141	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T236	15		T203	1		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T85	1		T140	15		T181	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T46	3		T153	1		T149	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T228	7		T145	5		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T35	1		T148	1		T53	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T5	1		T13	5		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T8	5		T142	1		T52	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T148	1		T233	9		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T35	1		T139	2		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T56	1		T152	1		T227	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T141	11		T228	15		T145	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	3		T16	3		T154	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T17	7		T105	14		T239	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T44	2		T32	12		T245	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T151	12		T145	1		T227	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	4		T17	11		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T45	1		T35	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T291	1		T155	15		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T183	1		T253	12		T203	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T187	15		T168	3		T238	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T144	12		T54	1		T236	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T236	13		T203	19		T169	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T140	13		T224	9		T243	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T153	8		T137	1		T259	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T228	6		T145	6		T172	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T260	9		T261	15		T262	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1076	1			T5	4		T15	9		T37	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	1		T52	2		T159	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T233	9		T146	6		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T139	8		T143	6		T144	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T56	9		T227	6		T171	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T228	14		T145	10		T138	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	1		T16	1		T161	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T17	2		T105	14		T156	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T32	4		T245	9		T254	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T145	2		T227	13		T102	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	2		T17	4		T153	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T170	14		T164	12		T102	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T291	12		T155	15		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T183	9		T253	12		T203	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T139	12		T102	8		T243	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T187	19		T195	13		T193	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T17	11		T291	1		T99	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T232	5		T253	12		T231	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T252	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T187	15		T250	8		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	1		T141	10		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T236	15		T168	3		T203	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T85	1		T140	15		T144	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T46	3		T153	1		T149	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T85	1		T228	7		T181	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T35	1		T53	6		T182	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	1		T39	2		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T8	5		T52	2		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T13	5		T14	1		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T35	1		T139	2		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T56	1		T152	1		T227	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T141	11		T196	1		T143	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	3		T16	3		T154	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T17	7		T100	15		T156	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T44	2		T32	12		T140	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T151	12		T145	1		T227	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T9	4		T153	1		T230	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T45	1		T35	1		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14544	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T17	4		T291	12		T323	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T253	12		T231	11		T245	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T187	19		T251	12		T324	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T139	12		T54	1		T236	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T236	13		T203	19		T169	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T140	13		T144	12		T224	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T153	8		T137	1		T263	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T228	6		T145	6		T172	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T247	2		T260	9		T259	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	4		T153	2		T233	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	1		T52	2		T159	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T15	9		T37	14		T233	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T139	8		T203	11		T105	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T56	9		T227	6		T187	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T143	6		T144	13		T228	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	1		T16	1		T256	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T17	2		T156	1		T175	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T32	4		T140	3		T161	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T145	2		T227	13		T102	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	2		T153	10		T230	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T170	14		T183	9		T164	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

3926

1

T5

4

T8

1

T9

2