Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23145

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19903

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3242

1

T9

6

T12

4

T17

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17259

1

T2

20

T3

20

T4

19

auto[1]

5886

1

T5

5

T8

6

T11

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19319

1

T2

20

T3

20

T4

19

auto[1]

3826

1

T8

1

T9

3

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	279	1			T17	15		T153	3		T148	1
values[0]	16	1			T224	14		T225	2		-	-
values[1]	630	1			T8	6		T152	1		T142	1
values[2]	690	1			T45	1		T85	1		T56	10
values[3]	675	1			T182	10		T227	25		T164	23
values[4]	2647	1			T9	6		T13	5		T14	1
values[5]	554	1			T5	5		T16	4		T139	7
values[6]	677	1			T139	3		T143	18		T227	21
values[7]	747	1			T11	1		T46	3		T35	2
values[8]	764	1			T153	11		T228	29		T137	4
values[9]	922	1			T12	4		T44	2		T17	9
minimum	14544	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	565	1			T45	1		T85	1		T152	1
values[1]	657	1			T56	10		T39	2		T144	28
values[2]	741	1			T52	4		T182	10		T183	10
values[3]	2632	1			T5	5		T9	6		T13	5
values[4]	645	1			T16	4		T139	7		T153	9
values[5]	589	1			T46	3		T139	3		T227	21
values[6]	772	1			T11	1		T35	2		T144	27
values[7]	692	1			T44	2		T17	9		T139	13
values[8]	909	1			T12	4		T17	15		T141	10
values[9]	168	1			T155	36		T235	14		T255	20
minimum	14775	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

3926

1

T5

4

T8

1

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T152	1		T140	14		T161	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T45	1		T85	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T229	1		T146	4		T187	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T56	10		T39	2		T144	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T52	4		T183	10		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T182	1		T227	7		T164	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T5	5		T13	1		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	4		T35	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T16	3		T153	9		T143	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T139	7		T196	1		T203	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T139	3		T232	1		T272	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T46	1		T227	12		T171	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	1		T35	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T35	1		T144	13		T145	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T44	2		T139	13		T228	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T17	3		T163	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T141	1		T153	14		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	3		T17	5		T32	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T155	18		T234	1		T325	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T235	14		T255	9		T326	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14511	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T142	1		T243	17		T235	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T140	14		T161	7		T105	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T149	9		T236	2		T187	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T229	10		T146	4		T187	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T144	14		T160	11		T237	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T168	14		T237	2		T269	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T182	9		T227	18		T164	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	932	1			T13	4		T141	10		T36	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	2		T228	6		T138	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T16	1		T143	11		T140	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T231	19		T238	2		T176	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T232	16		T73	4		T173	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T46	2		T227	9		T171	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T151	11		T41	5		T105	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T144	14		T145	12		T171	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T228	14		T137	1		T187	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T17	6		T145	4		T224	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T141	9		T233	27		T164	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	1		T17	10		T32	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T155	18		T234	4		T325	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T255	11		T327	10		T240	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	1		T9	1		T21	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T243	10		T244	12		T239	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T153	3		T148	1		T155	18
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T17	5		T54	3		T100	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T224	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T225	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	5		T152	1		T140	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T142	1		T159	15		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T229	1		T146	4		T230	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T45	1		T85	1		T56	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T187	6		T168	1		T237	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T182	1		T227	7		T164	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1416	1			T13	1		T14	1		T15	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T9	4		T35	1		T228	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	5		T16	3		T153	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T139	7		T142	1		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T139	3		T143	7		T232	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T227	12		T171	5		T203	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	1		T35	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T46	1		T35	1		T144	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T153	11		T228	15		T137	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T145	7		T224	20		T242	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T44	2		T141	1		T139	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T12	3		T17	3		T32	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T155	18		T43	7		T316	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T17	10		T54	2		T100	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T224	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T225	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	1		T140	14		T161	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T149	9		T236	2		T243	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T229	10		T146	4		T230	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T144	14		T160	11		T187	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T187	4		T168	14		T237	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T182	9		T227	18		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T13	4		T141	10		T36	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T9	2		T228	6		T138	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T16	1		T140	1		T149	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T231	19		T245	9		T255	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T143	11		T232	20		T168	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T227	9		T171	2		T102	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T151	11		T41	5		T105	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T46	2		T144	14		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T228	14		T137	1		T187	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T145	4		T224	11		T242	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T141	9		T233	27		T164	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	1		T17	6		T32	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T152	1		T140	15		T161	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T45	1		T85	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T229	11		T146	5		T187	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T56	1		T39	2		T144	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T52	2		T183	1		T168	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T182	10		T227	19		T164	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T5	1		T13	5		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	4		T35	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T16	3		T153	1		T143	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T139	1		T196	1		T203	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T139	1		T232	17		T272	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T46	3		T227	10		T171	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	1		T35	1		T151	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T35	1		T144	15		T145	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T44	2		T139	1		T228	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T17	7		T163	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T141	10		T153	2		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	3		T17	11		T32	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T155	19		T234	5		T325	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T235	1		T255	12		T326	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14638	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T142	1		T243	12		T235	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T140	13		T161	6		T169	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T159	14		T236	11		T187	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T146	3		T187	5		T230	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T56	9		T144	13		T170	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T52	2		T183	9		T237	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T227	6		T164	12		T203	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1064	1			T5	4		T15	9		T37	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T9	2		T228	6		T138	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T16	1		T153	8		T143	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T139	6		T203	21		T231	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T139	2		T73	2		T247	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T227	11		T171	4		T203	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T105	11		T248	13		T155	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T144	12		T145	10		T171	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T139	12		T228	14		T137	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T17	2		T145	6		T224	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T153	12		T233	23		T170	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	1		T17	4		T32	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T155	17		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T235	13		T255	8		T327	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T8	1		T236	13		T224	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T243	15		T235	12		T156	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T153	1		T148	1		T155	19
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T17	11		T54	4		T100	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T224	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T225	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T8	5		T152	1		T140	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T142	1		T159	1		T149	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T229	11		T146	5		T230	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T45	1		T85	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T187	5		T168	15		T237	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T182	10		T227	19		T164	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T13	5		T14	1		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	4		T35	1		T228	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	1		T16	3		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T139	1		T142	1		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T139	1		T143	12		T232	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T227	10		T171	3		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	1		T35	1		T151	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T46	3		T35	1		T144	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T153	1		T228	15		T137	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T145	5		T224	12		T242	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T44	2		T141	10		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	3		T17	7		T32	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14544	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T153	2		T155	17		T43	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T17	4		T54	1		T255	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T224	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	1		T140	13		T161	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T159	14		T236	11		T243	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T146	3		T230	12		T328	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T56	9		T144	13		T170	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T187	5		T237	6		T103	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T227	6		T164	12		T203	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1086	1			T15	9		T37	14		T52	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T9	2		T228	6		T138	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	4		T16	1		T153	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T139	6		T203	21		T231	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T139	2		T143	6		T73	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T227	11		T171	4		T203	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T105	11		T247	4		T24	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T144	12		T145	10		T171	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T153	10		T228	14		T137	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T145	6		T224	19		T102	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T139	12		T233	23		T170	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	1		T17	2		T32	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

3926

1

T5

4

T8

1

T9

2