Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23145

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19822

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3323

1

T8

6

T9

6

T44

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17333

1

T2

20

T3

20

T4

19

auto[1]

5812

1

T8

1

T9

6

T11

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19319

1

T2

20

T3

20

T4

19

auto[1]

3826

1

T8

1

T9

3

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	551	1			T5	5		T8	1		T12	6
values[0]	46	1			T93	1		T323	20		T319	1
values[1]	597	1			T141	11		T32	16		T228	29
values[2]	2567	1			T13	5		T14	1		T15	10
values[3]	639	1			T46	3		T139	10		T140	2
values[4]	674	1			T9	6		T85	1		T153	9
values[5]	692	1			T8	6		T85	1		T141	10
values[6]	622	1			T17	9		T149	7		T236	28
values[7]	720	1			T44	2		T16	4		T45	1
values[8]	594	1			T12	4		T17	15		T35	2
values[9]	1185	1			T11	1		T142	1		T148	1
minimum	14258	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	704	1			T32	16		T228	29		T53	6
values[1]	2570	1			T13	5		T14	1		T15	10
values[2]	654	1			T46	3		T85	1		T139	10
values[3]	655	1			T8	6		T9	6		T153	9
values[4]	693	1			T85	1		T141	10		T39	2
values[5]	645	1			T17	9		T140	28		T144	27
values[6]	689	1			T44	2		T16	4		T45	1
values[7]	682	1			T12	4		T17	15		T35	1
values[8]	1010	1			T5	5		T11	1		T56	10
values[9]	202	1			T233	34		T145	11		T73	11
minimum	14641	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

3926

1

T5

4

T8

1

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T32	5		T228	15		T53	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T168	2		T231	10		T291	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T13	1		T14	1		T15	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T35	1		T140	1		T146	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T242	1		T243	3		T268	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T46	1		T85	1		T139	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T153	9		T140	4		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T8	5		T9	4		T196	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T85	1		T39	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T141	1		T228	7		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T17	3		T144	13		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T140	14		T236	14		T187	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T16	3		T45	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T44	2		T229	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	3		T139	13		T153	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T17	5		T35	1		T153	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T5	5		T11	1		T56	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T142	1		T148	1		T54	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T145	7		T102	9		T231	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T233	15		T73	7		T204	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14476	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T231	12		T174	1		T329	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T32	11		T228	14		T53	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T168	16		T231	8		T268	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T13	4		T36	10		T201	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T140	1		T164	13		T187	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T242	5		T243	8		T268	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T46	2		T144	14		T269	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T140	3		T227	18		T253	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T8	1		T9	2		T224	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T154	12		T102	2		T243	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T141	9		T228	6		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T17	6		T144	14		T149	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T140	14		T236	14		T187	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T16	1		T145	12		T250	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T229	10		T160	11		T224	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	1		T182	9		T232	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T17	10		T143	11		T233	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T149	9		T137	1		T227	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T54	2		T168	14		T102	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T145	4		T102	5		T231	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T233	19		T73	4		T99	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	1		T141	10		T21	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T231	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	382	1			T5	5		T8	1		T12	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T233	15		T204	1		T235	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T323	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T93	1		T319	1		T320	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T141	1		T32	5		T228	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T168	2		T231	22		T291	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T13	1		T14	1		T15	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T35	1		T146	4		T237	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T164	13		T171	10		T242	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T46	1		T139	10		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T153	9		T140	4		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	4		T85	1		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T85	1		T39	2		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T8	5		T141	1		T228	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T17	3		T149	1		T138	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T236	14		T187	7		T155	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T16	3		T45	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T44	2		T140	14		T229	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	3		T35	1		T139	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T17	5		T35	1		T153	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T11	1		T149	1		T137	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T142	1		T148	1		T54	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14149	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T145	4		T237	11		T258	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T233	19		T297	2		T307	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T323	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T320	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T141	10		T32	11		T228	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T168	16		T231	17		T268	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T13	4		T36	10		T201	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T237	2		T105	17		T245	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T164	10		T171	5		T242	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T46	2		T140	1		T144	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T140	3		T227	18		T253	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T9	2		T269	10		T90	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T154	12		T102	2		T243	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T8	1		T141	9		T228	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T17	6		T149	6		T138	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T236	14		T187	5		T155	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T16	1		T144	14		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T140	14		T229	10		T160	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	1		T182	9		T232	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T17	10		T143	11		T233	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T149	9		T137	1		T227	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T54	2		T168	14		T230	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T32	12		T228	15		T53	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T168	18		T231	9		T291	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T13	5		T14	1		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T35	1		T140	2		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T242	6		T243	9		T268	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T46	3		T85	1		T139	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T153	1		T140	4		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	5		T9	4		T196	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T85	1		T39	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T141	10		T228	7		T151	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T17	7		T144	15		T149	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T140	15		T236	15		T187	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T16	3		T45	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T44	2		T229	11		T160	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	3		T139	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T17	11		T35	1		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T5	1		T11	1		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T142	1		T148	1		T54	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T145	5		T102	6		T231	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T233	20		T73	9		T204	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14588	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T231	10		T174	1		T329	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T32	4		T228	14		T161	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T231	9		T291	12		T273	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1080	1			T15	9		T37	14		T170	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T146	3		T164	12		T187	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T243	2		T282	14		T330	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T139	8		T144	13		T269	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T153	8		T140	3		T227	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	1		T9	2		T159	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T159	14		T169	10		T102	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T228	6		T309	23		T156	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T17	2		T144	12		T138	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T140	13		T236	13		T187	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T16	1		T145	12		T331	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T203	11		T224	9		T245	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	1		T139	12		T153	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T17	4		T153	10		T143	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	4		T56	9		T137	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T54	1		T102	10		T248	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T145	6		T102	8		T231	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T233	14		T73	2		T332	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T171	4		T275	7		T24	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T231	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T5	1		T8	1		T12	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T233	20		T204	1		T235	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T323	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T93	1		T319	1		T320	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T141	11		T32	12		T228	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T168	18		T231	19		T291	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T13	5		T14	1		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T35	1		T146	1		T237	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T164	11		T171	6		T242	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T46	3		T139	2		T140	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T153	1		T140	4		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	4		T85	1		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T85	1		T39	2		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	5		T141	10		T228	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T17	7		T149	7		T138	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T236	15		T187	7		T155	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T16	3		T45	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T44	2		T140	15		T229	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	3		T35	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T17	11		T35	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T11	1		T149	10		T137	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T142	1		T148	1		T54	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14258	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T5	4		T56	9		T145	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T233	14		T235	14		T297	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T323	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T320	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T32	4		T228	14		T227	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T231	20		T291	12		T316	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1061	1			T15	9		T37	14		T161	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T146	3		T237	6		T203	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T164	12		T171	9		T105	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T139	8		T144	13		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T153	8		T140	3		T227	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	2		T159	12		T203	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T159	14		T102	4		T243	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	1		T228	6		T170	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T17	2		T138	1		T169	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T236	13		T187	5		T155	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T16	1		T144	12		T145	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T140	13		T203	11		T224	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	1		T139	12		T153	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T17	4		T153	10		T143	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T137	1		T183	9		T227	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T54	1		T230	12		T73	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

3926

1

T5

4

T8

1

T9

2