Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23145

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19696

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3449

1

T5

5

T9

6

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17708

1

T2

20

T3

20

T4

19

auto[1]

5437

1

T8

6

T9

6

T44

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19319

1

T2

20

T3

20

T4

19

auto[1]

3826

1

T8

1

T9

3

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	176	1			T148	1		T161	14		T172	13
values[0]	88	1			T153	9		T255	17		T262	19
values[1]	680	1			T35	1		T196	1		T154	13
values[2]	603	1			T153	11		T142	1		T144	28
values[3]	756	1			T16	4		T17	9		T45	1
values[4]	725	1			T12	4		T85	1		T32	16
values[5]	2832	1			T13	5		T14	1		T15	10
values[6]	663	1			T5	5		T9	6		T56	10
values[7]	549	1			T44	2		T17	15		T152	1
values[8]	685	1			T11	1		T141	11		T139	7
values[9]	844	1			T8	6		T39	2		T140	28
minimum	14544	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	666	1			T35	1		T153	11		T154	13
values[1]	635	1			T16	4		T85	1		T142	1
values[2]	766	1			T17	9		T45	1		T46	3
values[3]	2916	1			T12	4		T13	5		T14	1
values[4]	640	1			T5	5		T9	6		T52	4
values[5]	614	1			T44	2		T17	15		T56	10
values[6]	668	1			T35	1		T139	7		T142	1
values[7]	632	1			T11	1		T141	11		T140	7
values[8]	764	1			T8	6		T39	2		T140	28
values[9]	80	1			T159	13		T204	1		T165	8
minimum	14764	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

3926

1

T5

4

T8

1

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T153	11		T154	1		T181	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	1		T144	14		T159	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T236	14		T237	7		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T16	3		T85	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T45	1		T46	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T17	3		T139	16		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1495	1			T12	3		T13	1		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T85	1		T35	1		T233	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T52	4		T145	3		T242	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	5		T9	4		T228	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T44	2		T56	10		T227	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T17	5		T152	1		T228	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T35	1		T140	1		T145	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T139	7		T142	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T140	4		T137	3		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	1		T141	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	5		T39	2		T140	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T148	1		T53	4		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T159	13		T306	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T204	1		T165	1		T189	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14504	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T164	13		T333	1		T280	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T154	12		T227	18		T171	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T144	14		T155	18		T173	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T236	14		T237	2		T165	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T16	1		T171	12		T269	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T46	2		T141	9		T143	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T17	6		T227	14		T187	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T12	1		T13	4		T32	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T233	19		T151	11		T232	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T242	5		T231	9		T250	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	2		T228	14		T187	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T227	9		T168	2		T105	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T17	10		T228	6		T149	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T140	1		T145	12		T232	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T145	4		T168	14		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T140	3		T137	1		T230	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T141	10		T138	1		T248	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	1		T140	14		T161	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T53	2		T149	6		T160	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T306	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T165	7		T189	13		T334	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	1		T21	4		T39	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T164	13		T280	10		T335	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T161	7		T172	13		T238	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T148	1		T204	1		T243	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T153	9		T255	8		T262	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T304	1		T308	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T196	1		T154	1		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T35	1		T164	13		T272	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T153	11		T181	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T142	1		T144	14		T159	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T45	1		T46	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T16	3		T17	3		T85	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	3		T32	5		T236	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T85	1		T35	1		T233	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1450	1			T13	1		T14	1		T15	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T146	4		T232	1		T187	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T56	10		T227	12		T105	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	5		T9	4		T228	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T44	2		T35	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T17	5		T152	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T140	5		T137	3		T145	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	1		T141	1		T139	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T8	5		T39	2		T140	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T53	4		T149	1		T160	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T161	7		T238	1		T306	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T243	2		T165	7		T189	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T255	9		T262	14		T290	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T304	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T154	12		T229	10		T227	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T164	13		T155	18		T173	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T165	5		T99	10		T283	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T144	14		T171	12		T269	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T46	2		T141	9		T143	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T16	1		T17	6		T227	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	1		T32	11		T236	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T233	19		T151	11		T254	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T13	4		T36	10		T201	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T232	4		T187	4		T41	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T227	9		T105	13		T245	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	2		T228	20		T149	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T232	16		T168	2		T253	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T17	10		T237	11		T239	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T140	4		T137	1		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T141	10		T145	4		T138	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	1		T140	14		T168	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T53	2		T149	6		T160	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T153	1		T154	13		T181	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T35	1		T144	15		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T236	15		T237	3		T165	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T16	3		T85	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T45	1		T46	3		T141	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T17	7		T139	2		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T12	3		T13	5		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T85	1		T35	1		T233	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T52	2		T145	1		T242	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	1		T9	4		T228	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T44	2		T56	1		T227	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T17	11		T152	1		T228	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T35	1		T140	2		T145	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T139	1		T142	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T140	4		T137	3		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	1		T141	11		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	5		T39	2		T140	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T148	1		T53	6		T149	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T159	1		T306	10		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T204	1		T165	8		T189	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14596	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T164	14		T333	1		T280	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T153	10		T183	9		T227	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T144	13		T159	14		T155	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T236	13		T237	6		T283	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T16	1		T171	17		T269	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T143	6		T144	12		T54	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T17	2		T139	14		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T12	1		T15	9		T32	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T233	14		T203	21		T248	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T52	2		T145	2		T231	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	4		T9	2		T228	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T56	9		T227	11		T105	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T17	4		T228	6		T146	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T145	10		T253	12		T203	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T139	6		T170	14		T145	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T140	3		T137	1		T230	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T138	1		T248	13		T243	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	1		T140	13		T161	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T170	15		T256	10		T258	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T159	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T311	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T153	8		T255	7		T177	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T164	12		T280	14		T308	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T161	8		T172	1		T238	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T148	1		T204	1		T243	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T153	1		T255	10		T262	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T304	2		T308	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T196	1		T154	13		T229	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T35	1		T164	14		T272	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T153	1		T181	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T142	1		T144	15		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T45	1		T46	3		T141	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	3		T17	7		T85	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	3		T32	12		T236	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T85	1		T35	1		T233	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T13	5		T14	1		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T146	1		T232	5		T187	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T56	1		T227	10		T105	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	1		T9	4		T228	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T44	2		T35	1		T232	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T17	11		T152	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T140	6		T137	3		T145	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	1		T141	11		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T8	5		T39	2		T140	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T53	6		T149	7		T160	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14544	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T161	6		T172	12		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T243	13		T261	10		T336	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T153	8		T255	7		T262	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T308	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T183	9		T227	6		T171	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T164	12		T155	17		T173	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T153	10		T283	7		T303	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T144	13		T159	14		T171	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T143	6		T144	12		T54	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T16	1		T17	2		T139	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T32	4		T236	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T233	14		T203	21		T254	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1113	1			T15	9		T37	14		T52	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T146	3		T187	5		T73	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T56	9		T227	11		T105	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	4		T9	2		T228	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T253	12		T203	11		T102	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T17	4		T237	13		T155	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T140	3		T137	1		T145	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T139	6		T170	14		T145	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	1		T140	13		T159	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T170	15		T256	10		T258	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

3926

1

T5

4

T8

1

T9

2