Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T252	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T250	1		T251	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	1		T141	1		T139	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T236	26		T187	20		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T85	1		T153	9		T144	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T46	1		T149	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T85	1		T140	14		T228	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T35	1		T53	4		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T39	2		T153	3		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	5		T8	5		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T13	1		T14	1		T15	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T139	3		T143	7		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T56	10		T141	1		T227	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T152	1		T35	1		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	3		T17	3		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T16	3		T100	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T32	5		T140	4		T245	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T44	2		T151	1		T161	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	428	1			T17	5		T153	11		T230	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T9	4		T45	1		T35	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T2	20		T3	20		T4	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T252	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T250	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T141	9		T41	12		T102	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T236	16		T187	14		T168	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T144	14		T54	2		T224	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T46	2		T149	9		T160	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T140	14		T228	6		T145	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T53	2		T182	9		T165	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T140	1		T233	19		T149	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	1		T229	10		T171	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	914	1			T13	4		T36	10		T201	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T143	11		T258	1		T103	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T141	10		T227	18		T171	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T144	14		T228	14		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	1		T17	6		T154	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T16	1		T100	14		T175	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T32	11		T140	3		T245	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T151	11		T161	7		T227	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T17	10		T230	8		T41	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T9	2		T232	4		T164	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	1		T85	1		T141	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T236	15		T187	15		T168	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T85	1		T153	1		T140	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T46	3		T149	10		T160	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T39	2		T148	1		T228	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T35	1		T53	6		T182	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T13	5		T14	1		T15	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T5	1		T8	5		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T139	1		T233	9		T146	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T35	1		T139	1		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T56	1		T227	19		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T152	1		T145	13		T138	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	3		T17	7		T141	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T16	3		T105	14		T239	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T32	12		T245	10		T254	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T44	2		T151	12		T161	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T17	11		T153	1		T140	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	4		T45	1		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T203	1		T155	15		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T183	1		T253	12		T255	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14544	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T236	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T139	12		T144	12		T41	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T236	13		T187	19		T203	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T153	8		T140	13		T54	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T137	1		T157	1		T259	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T228	6		T145	6		T172	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T260	9		T261	15		T262	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T15	9		T37	14		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	4		T8	1		T52	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T139	6		T233	9		T146	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T139	2		T143	6		T144	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T56	9		T227	6		T256	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T145	10		T138	1		T105	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	1		T17	2		T237	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T16	1		T105	14		T156	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T32	4		T245	9		T254	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T161	6		T145	2		T227	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T17	4		T153	10		T140	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	2		T170	14		T164	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T203	21		T155	15		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T183	9		T253	12		T255	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T236	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T252	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T250	8		T251	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	1		T141	10		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T236	18		T187	15		T168	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T85	1		T153	1		T144	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T46	3		T149	10		T160	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T85	1		T140	15		T228	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T35	1		T53	6		T182	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T39	2		T153	1		T140	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	1		T8	5		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T13	5		T14	1		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T139	1		T143	12		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T56	1		T141	11		T227	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T152	1		T35	1		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	3		T17	7		T154	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T16	3		T100	15		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T32	12		T140	4		T245	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T44	2		T151	12		T161	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T17	11		T153	1		T230	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T9	4		T45	1		T35	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14544	1			T2	20		T3	20		T4	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T251	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T139	12		T170	15		T41	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T236	24		T187	19		T203	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T153	8		T144	12		T54	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T137	1		T263	10		T261	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T140	13		T228	6		T145	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T247	2		T157	1		T260	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T153	2		T233	14		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	4		T8	1		T52	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1066	1			T15	9		T37	14		T139	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T139	2		T143	6		T159	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T56	9		T227	6		T171	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T144	13		T228	14		T145	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	1		T17	2		T256	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T16	1		T175	1		T264	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T32	4		T140	3		T245	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T161	6		T145	2		T227	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	363	1			T17	4		T153	10		T230	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	2		T170	14		T183	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

3926

1

T5

4

T8

1

T9

2