Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23145

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19800

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3345

1

T5

5

T9

6

T16

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17590

1

T2

20

T3

20

T4

19

auto[1]

5555

1

T8

6

T11

1

T12

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19319

1

T2

20

T3

20

T4

19

auto[1]

3826

1

T8

1

T9

3

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T265	1		T266	22		-	-
values[0]	30	1			T247	16		T189	14		-	-
values[1]	609	1			T39	2		T153	11		T228	13
values[2]	609	1			T5	5		T16	4		T32	16
values[3]	883	1			T11	1		T17	9		T140	2
values[4]	665	1			T141	10		T139	13		T142	1
values[5]	554	1			T46	3		T85	1		T56	10
values[6]	705	1			T12	4		T44	2		T17	15
values[7]	746	1			T45	1		T142	1		T196	1
values[8]	710	1			T8	6		T85	1		T35	1
values[9]	3067	1			T9	6		T13	5		T14	1
minimum	14544	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	838	1			T39	2		T153	20		T228	13
values[1]	702	1			T5	5		T11	1		T16	4
values[2]	853	1			T17	9		T141	10		T139	13
values[3]	489	1			T46	3		T85	1		T142	1
values[4]	760	1			T12	4		T44	2		T17	15
values[5]	540	1			T152	1		T35	2		T139	3
values[6]	2854	1			T8	6		T13	5		T14	1
values[7]	736	1			T148	2		T227	46		T147	1
values[8]	695	1			T141	11		T139	7		T52	4
values[9]	134	1			T9	6		T170	16		T181	1
minimum	14544	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

3926

1

T5

4

T8

1

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T39	2		T153	11		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T153	9		T228	7		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	1		T32	5		T159	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	5		T16	3		T144	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T139	13		T140	5		T144	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T17	3		T141	1		T159	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T46	1		T85	1		T256	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T142	1		T145	11		T232	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	3		T44	2		T17	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T153	3		T143	7		T140	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T139	3		T196	1		T187	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T152	1		T35	2		T54	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T8	5		T13	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T45	1		T35	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T148	2		T227	19		T187	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T147	1		T187	20		T171	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T139	7		T233	10		T231	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T141	1		T52	4		T137	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T170	16		T22	1		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T9	4		T181	1		T248	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T2	20		T3	20		T4	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T151	11		T224	11		T231	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T228	6		T149	9		T245	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T32	11		T171	5		T242	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T16	1		T144	14		T160	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T140	4		T144	14		T168	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T17	6		T141	9		T138	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T46	2		T256	6		T102	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T145	12		T232	16		T41	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T12	1		T17	10		T53	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T143	11		T140	14		T228	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T187	1		T253	11		T224	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T54	2		T146	4		T164	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T8	1		T13	4		T36	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T154	12		T229	10		T149	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T227	27		T187	4		T239	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T187	14		T171	7		T243	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T233	8		T231	11		T239	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T141	10		T137	1		T168	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T100	14		T205	8		T267	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T9	2		T248	4		T176	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T265	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T266	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T247	6		T189	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T39	2		T153	11		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T228	7		T149	1		T170	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T32	5		T145	3		T102	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	5		T16	3		T153	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T11	1		T140	1		T144	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T17	3		T144	13		T159	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T139	13		T140	4		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T141	1		T142	1		T145	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T46	1		T85	1		T56	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T153	3		T143	7		T140	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	3		T44	2		T17	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T152	1		T35	2		T233	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T142	1		T196	1		T161	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T45	1		T154	1		T229	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T8	5		T85	1		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T35	1		T183	10		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1533	1			T13	1		T14	1		T15	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T9	4		T141	1		T52	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T266	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T247	10		T189	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T151	11		T224	11		T231	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T228	6		T149	9		T245	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T32	11		T102	2		T268	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T16	1		T160	11		T269	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T140	1		T144	14		T171	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T17	6		T144	14		T145	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T140	3		T256	6		T102	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T141	9		T145	12		T232	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T46	2		T53	2		T232	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T143	11		T140	14		T228	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	1		T17	10		T187	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T233	19		T146	4		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T161	7		T182	9		T168	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T154	12		T229	10		T149	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	1		T227	23		T187	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T187	14		T171	7		T243	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T13	4		T36	10		T201	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	2		T141	10		T137	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T39	2		T153	1		T151	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T153	1		T228	7		T149	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	1		T32	12		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	1		T16	3		T144	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T139	1		T140	6		T144	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T17	7		T141	10		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T46	3		T85	1		T256	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T142	1		T145	13		T232	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	3		T44	2		T17	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T153	1		T143	12		T140	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T139	1		T196	1		T187	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T152	1		T35	2		T54	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T8	5		T13	5		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T45	1		T35	1		T154	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T148	2		T227	29		T187	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T147	1		T187	15		T171	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T139	1		T233	9		T231	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T141	11		T52	2		T137	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T170	1		T22	1		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T9	4		T181	1		T248	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14544	1			T2	20		T3	20		T4	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T153	10		T146	3		T224	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T153	8		T228	6		T170	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T32	4		T159	14		T145	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	4		T16	1		T144	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T139	12		T140	3		T144	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T17	2		T159	12		T138	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T256	10		T102	10		T255	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T145	10		T41	8		T203	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	1		T17	4		T56	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T153	2		T143	6		T140	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T139	2		T253	12		T224	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T54	1		T146	3		T164	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T8	1		T15	9		T37	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T236	24		T183	9		T156	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T227	17		T187	5		T203	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T187	19		T171	8		T203	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T139	6		T233	9		T231	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T52	2		T137	1		T172	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T170	15		T270	11		T271	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T9	2		T248	5		T176	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T265	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T266	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T247	11		T189	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T39	2		T153	1		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T228	7		T149	10		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T32	12		T145	1		T102	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	1		T16	3		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	1		T140	2		T144	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T17	7		T144	15		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T139	1		T140	4		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T141	10		T142	1		T145	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T46	3		T85	1		T56	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T153	1		T143	12		T140	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	3		T44	2		T17	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T152	1		T35	2		T233	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T142	1		T196	1		T161	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T45	1		T154	13		T229	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	5		T85	1		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T35	1		T183	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T13	5		T14	1		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T9	4		T141	11		T52	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14544	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T266	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T247	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T153	10		T146	3		T224	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T228	6		T170	14		T245	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T32	4		T145	2		T102	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	4		T16	1		T153	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T144	13		T159	14		T171	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T17	2		T144	12		T159	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T139	12		T140	3		T256	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T145	10		T138	1		T237	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T56	9		T249	9		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T153	2		T143	6		T140	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	1		T17	4		T139	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T233	14		T146	3		T237	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T161	6		T258	1		T173	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T54	1		T236	24		T164	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	1		T227	24		T187	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T183	9		T187	19		T171	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T15	9		T37	14		T139	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T9	2		T52	2		T137	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

3926

1

T5

4

T8

1

T9

2