Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23145

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19810

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3335

1

T5

5

T9

6

T12

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17487

1

T2

20

T3

20

T4

19

auto[1]

5658

1

T8

6

T11

1

T44

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19319

1

T2

20

T3

20

T4

19

auto[1]

3826

1

T8

1

T9

3

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	191	1			T9	6		T22	1		T168	3
values[0]	2	1			T39	2		-	-		-	-
values[1]	654	1			T153	11		T228	13		T149	10
values[2]	572	1			T5	5		T16	4		T32	16
values[3]	929	1			T11	1		T17	9		T140	2
values[4]	698	1			T141	10		T139	13		T142	1
values[5]	578	1			T17	15		T46	3		T85	1
values[6]	647	1			T12	4		T44	2		T152	1
values[7]	739	1			T45	1		T142	1		T196	1
values[8]	679	1			T8	6		T85	1		T35	1
values[9]	2912	1			T13	5		T14	1		T15	10
minimum	14544	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	660	1			T153	11		T228	13		T149	10
values[1]	674	1			T5	5		T16	4		T32	16
values[2]	808	1			T11	1		T17	9		T141	10
values[3]	550	1			T85	1		T142	1		T145	23
values[4]	741	1			T12	4		T17	15		T46	3
values[5]	536	1			T44	2		T152	1		T35	2
values[6]	2797	1			T8	6		T13	5		T14	1
values[7]	816	1			T148	2		T236	14		T227	74
values[8]	730	1			T141	11		T139	7		T52	4
values[9]	82	1			T9	6		T181	1		T22	1
minimum	14751	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

3926

1

T5

4

T8

1

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T153	11		T146	4		T224	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T228	7		T149	1		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T159	15		T160	1		T145	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	5		T16	3		T32	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	1		T139	13		T140	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T17	3		T141	1		T159	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T85	1		T147	1		T256	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T142	1		T145	11		T232	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T17	5		T46	1		T56	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T12	3		T153	3		T143	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T44	2		T139	3		T164	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T152	1		T35	2		T54	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T8	5		T13	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T45	1		T35	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T148	2		T227	19		T203	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T236	12		T227	14		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T139	7		T233	10		T170	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T141	1		T52	4		T137	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T22	1		T204	1		T205	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T9	4		T181	1		T248	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14478	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T245	10		T273	16		T90	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T224	11		T234	2		T289	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T228	6		T149	9		T151	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T171	7		T242	5		T102	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T16	1		T32	11		T144	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T140	4		T144	14		T164	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T17	6		T141	9		T138	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T256	6		T165	7		T268	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T145	12		T232	16		T237	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T17	10		T46	2		T232	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	1		T143	11		T140	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T164	13		T187	1		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T54	2		T146	4		T99	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T8	1		T13	4		T36	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T154	12		T229	10		T149	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T227	27		T239	8		T247	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T236	2		T227	14		T187	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T233	8		T187	4		T231	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T141	10		T137	1		T168	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T205	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T9	2		T248	4		T176	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	1		T21	4		T39	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T245	9		T90	2		T290	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T22	1		T260	10		T263	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T9	4		T168	1		T248	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T39	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T153	11		T146	4		T224	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T228	7		T149	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T160	1		T145	3		T171	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	5		T16	3		T32	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T11	1		T140	1		T144	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T17	3		T144	13		T159	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T139	13		T140	4		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T141	1		T142	1		T145	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T17	5		T46	1		T85	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T153	3		T143	7		T140	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T44	2		T139	3		T187	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	3		T152	1		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T142	1		T196	1		T161	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T45	1		T154	1		T229	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T8	5		T85	1		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T35	1		T236	12		T183	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1502	1			T13	1		T14	1		T15	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T141	1		T52	4		T137	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T260	10		T280	4		T30	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T9	2		T168	2		T248	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T224	11		T231	9		T247	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T228	6		T149	9		T151	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T171	2		T102	2		T268	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T16	1		T32	11		T160	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T140	1		T144	14		T164	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T17	6		T144	14		T145	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T140	3		T256	6		T165	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T141	9		T145	12		T232	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T17	10		T46	2		T232	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T143	11		T140	14		T228	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T187	1		T253	11		T224	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	1		T233	19		T54	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T161	7		T182	9		T164	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T154	12		T229	10		T149	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T8	1		T227	9		T187	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T236	2		T227	14		T187	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T13	4		T36	10		T201	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T141	10		T137	1		T41	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T153	1		T146	1		T224	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T228	7		T149	10		T151	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T159	1		T160	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	1		T16	3		T32	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	1		T139	1		T140	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T17	7		T141	10		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T85	1		T147	1		T256	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T142	1		T145	13		T232	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T17	11		T46	3		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	3		T153	1		T143	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T44	2		T139	1		T164	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T152	1		T35	2		T54	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T8	5		T13	5		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T45	1		T35	1		T154	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T148	2		T227	29		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T236	3		T227	15		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T139	1		T233	9		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T141	11		T52	2		T137	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T22	1		T204	1		T205	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T9	4		T181	1		T248	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14609	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T245	10		T273	1		T90	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T153	10		T146	3		T224	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T228	6		T170	14		T245	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T159	14		T145	2		T171	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	4		T16	1		T32	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T139	12		T140	3		T144	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T17	2		T159	12		T138	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T256	10		T235	13		T255	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T145	10		T237	6		T41	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T17	4		T56	9		T291	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	1		T153	2		T143	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T139	2		T164	12		T253	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T54	1		T146	3		T169	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T8	1		T15	9		T37	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T236	13		T183	9		T259	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T227	17		T203	19		T247	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T236	11		T227	13		T187	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T139	6		T233	9		T170	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T52	2		T137	1		T172	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T270	11		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T9	2		T248	5		T176	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T231	11		T247	5		T216	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T245	9		T273	15		T90	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T22	1		T260	11		T263	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T9	4		T168	3		T248	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T39	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T153	1		T146	1		T224	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T228	7		T149	10		T151	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T160	1		T145	1		T171	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	1		T16	3		T32	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	1		T140	2		T144	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T17	7		T144	15		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T139	1		T140	4		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T141	10		T142	1		T145	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T17	11		T46	3		T85	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T153	1		T143	12		T140	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T44	2		T139	1		T187	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	3		T152	1		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T142	1		T196	1		T161	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T45	1		T154	13		T229	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T8	5		T85	1		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T35	1		T236	3		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T13	5		T14	1		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T141	11		T52	2		T137	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14544	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T260	9		T263	10		T280	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T9	2		T248	13		T261	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T153	10		T146	3		T224	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T228	6		T170	14		T245	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T145	2		T171	4		T102	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T5	4		T16	1		T32	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T144	13		T159	14		T164	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T17	2		T144	12		T159	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T139	12		T140	3		T256	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T145	10		T138	1		T237	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T17	4		T56	9		T249	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T153	2		T143	6		T140	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T139	2		T253	12		T224	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T233	14		T54	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T161	6		T164	12		T258	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T236	13		T259	5		T262	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	1		T227	11		T187	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T236	11		T183	9		T227	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T15	9		T37	14		T139	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T52	2		T137	1		T203	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

3926

1

T5

4

T8

1

T9

2