Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23145

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19834

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3311

1

T9

6

T11

1

T44

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17558

1

T2

20

T3

20

T4

19

auto[1]

5587

1

T8

6

T44

2

T13

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19319

1

T2

20

T3

20

T4

19

auto[1]

3826

1

T8

1

T9

3

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	304	1			T11	1		T17	15		T152	1
values[0]	18	1			T292	18		-	-		-	-
values[1]	690	1			T5	5		T44	2		T85	1
values[2]	584	1			T161	14		T168	3		T41	21
values[3]	632	1			T12	4		T39	2		T142	1
values[4]	578	1			T154	13		T140	28		T145	23
values[5]	733	1			T46	3		T153	3		T148	1
values[6]	626	1			T139	13		T228	13		T160	12
values[7]	761	1			T8	6		T45	1		T35	1
values[8]	2726	1			T13	5		T14	1		T15	10
values[9]	949	1			T9	6		T85	1		T56	10
minimum	14544	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	661	1			T44	2		T141	10		T35	1
values[1]	629	1			T144	27		T161	14		T171	7
values[2]	627	1			T12	4		T39	2		T142	1
values[3]	534	1			T153	3		T154	13		T140	28
values[4]	783	1			T46	3		T139	13		T53	6
values[5]	747	1			T8	6		T139	3		T196	1
values[6]	2674	1			T13	5		T14	1		T15	10
values[7]	783	1			T17	9		T139	7		T153	11
values[8]	842	1			T9	6		T17	15		T85	1
values[9]	150	1			T11	1		T35	1		T140	2
minimum	14715	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

3926

1

T5

4

T8

1

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T35	1		T153	9		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T44	2		T141	1		T227	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T144	13		T161	7		T171	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T41	9		T253	13		T224	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	3		T148	1		T236	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T39	2		T142	1		T233	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T153	3		T154	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T140	14		T147	1		T237	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T139	13		T53	4		T170	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T46	1		T160	1		T187	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T8	5		T196	1		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T139	3		T143	7		T228	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1418	1			T13	1		T14	1		T15	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T35	1		T52	4		T159	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T17	3		T139	7		T153	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T140	4		T237	14		T41	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T17	5		T152	1		T236	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T9	4		T85	1		T56	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T35	1		T140	1		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T11	1		T289	14		T293	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14507	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T85	1		T144	14		T183	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T54	2		T256	6		T231	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T141	9		T227	9		T138	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T144	14		T161	7		T171	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T41	12		T253	11		T224	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T12	1		T236	14		T105	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T233	27		T137	1		T227	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T154	12		T145	12		T146	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T140	14		T237	2		T102	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T53	2		T232	16		T168	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T46	2		T187	14		T239	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	1		T160	11		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T143	11		T228	6		T90	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T13	4		T16	1		T36	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T229	10		T149	6		T258	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T17	6		T171	5		T102	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T140	3		T237	11		T41	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T17	10		T236	2		T227	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	2		T141	10		T32	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T140	1		T182	9		T145	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T289	5		T293	10		T294	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	1		T21	4		T39	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T144	14		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T17	5		T152	1		T182	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T11	1		T232	1		T295	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T292	18		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	5		T35	1		T153	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T44	2		T85	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T161	7		T168	1		T231	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T41	9		T253	13		T224	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	3		T148	1		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T39	2		T142	1		T233	25
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T154	1		T145	11		T164	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T140	14		T227	14		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T153	3		T148	1		T53	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T46	1		T160	1		T187	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T139	13		T160	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T228	7		T22	1		T90	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T8	5		T45	1		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T35	1		T139	3		T143	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1441	1			T13	1		T14	1		T15	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T52	4		T41	1		T172	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T35	1		T139	7		T153	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T9	4		T85	1		T56	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T17	10		T182	9		T145	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T232	4		T290	2		T289	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T54	2		T256	6		T205	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T141	9		T144	14		T227	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T161	7		T168	2		T231	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T41	12		T253	11		T224	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T12	1		T144	14		T236	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T233	27		T137	1		T164	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T154	12		T145	12		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T140	14		T227	14		T242	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T53	2		T146	4		T168	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T46	2		T187	14		T237	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T160	11		T151	11		T232	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T228	6		T90	2		T247	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T8	1		T187	4		T168	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T143	11		T229	10		T149	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T13	4		T16	1		T17	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T41	5		T155	14		T268	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T140	1		T236	2		T227	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	2		T141	10		T32	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T35	1		T153	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T44	2		T141	10		T227	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T144	15		T161	8		T171	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T41	13		T253	12		T224	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	3		T148	1		T236	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T39	2		T142	1		T233	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T153	1		T154	13		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T140	15		T147	1		T237	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T139	1		T53	6		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T46	3		T160	1		T187	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T8	5		T196	1		T160	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T139	1		T143	12		T228	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T13	5		T14	1		T15	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T35	1		T52	2		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T17	7		T139	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T140	4		T237	12		T41	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T17	11		T152	1		T236	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T9	4		T85	1		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T35	1		T140	2		T182	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T11	1		T289	6		T293	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14601	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T85	1		T144	15		T183	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T153	8		T54	1		T145	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T227	11		T138	1		T243	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T144	12		T161	6		T171	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T41	8		T253	12		T224	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	1		T236	13		T169	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T233	23		T137	1		T227	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T153	2		T145	10		T146	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T140	13		T237	6		T102	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T139	12		T170	14		T203	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T187	19		T296	11		T251	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	1		T187	5		T224	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T139	2		T143	6		T228	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1085	1			T15	9		T16	1		T37	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T52	2		T159	12		T258	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T17	2		T139	6		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T140	3		T237	13		T172	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T17	4		T236	11		T227	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T9	2		T56	9		T32	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T145	6		T102	10		T297	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T289	13		T293	11		T193	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T5	4		T172	12		T280	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T144	13		T183	9		T203	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T17	11		T152	1		T182	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T11	1		T232	5		T295	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T292	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	1		T35	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T44	2		T85	1		T141	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T161	8		T168	3		T231	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T41	13		T253	12		T224	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	3		T148	1		T144	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T39	2		T142	1		T233	29
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T154	13		T145	13		T164	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T140	15		T227	15		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T153	1		T148	1		T53	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T46	3		T160	1		T187	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T139	1		T160	12		T151	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T228	7		T22	1		T90	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T8	5		T45	1		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T35	1		T139	1		T143	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T13	5		T14	1		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T52	2		T41	6		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T35	1		T139	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T9	4		T85	1		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14544	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T17	4		T145	6		T102	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T290	18		T289	13		T298	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T292	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	4		T153	8		T54	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T144	13		T183	9		T227	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T161	6		T231	10		T245	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T41	8		T253	12		T224	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	1		T144	12		T236	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T233	23		T137	1		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T145	10		T164	12		T169	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T140	13		T227	13		T102	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T153	2		T170	14		T146	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T187	19		T237	6		T296	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T139	12		T254	1		T259	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T228	6		T90	2		T247	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T187	5		T224	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T139	2		T143	6		T159	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1107	1			T15	9		T16	1		T17	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T52	2		T172	13		T155	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T139	6		T153	10		T236	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T9	2		T56	9		T32	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

3926

1

T5

4

T8

1

T9

2