Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23145

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19753

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3392

1

T9

6

T11

1

T44

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17570

1

T2

20

T3

20

T4

19

auto[1]

5575

1

T8

6

T44

2

T13

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19319

1

T2

20

T3

20

T4

19

auto[1]

3826

1

T8

1

T9

3

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	53	1			T35	1		T140	2		T182	10
values[0]	25	1			T299	3		T300	4		T292	18
values[1]	745	1			T5	5		T44	2		T85	1
values[2]	491	1			T161	14		T41	21		T253	24
values[3]	636	1			T39	2		T142	1		T148	1
values[4]	600	1			T12	4		T154	13		T140	28
values[5]	752	1			T46	3		T153	3		T148	1
values[6]	620	1			T139	13		T228	13		T160	12
values[7]	760	1			T8	6		T45	1		T139	3
values[8]	2676	1			T13	5		T14	1		T15	10
values[9]	1243	1			T9	6		T11	1		T17	15
minimum	14544	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	816	1			T5	5		T44	2		T85	1
values[1]	639	1			T144	27		T161	14		T171	7
values[2]	565	1			T12	4		T39	2		T142	1
values[3]	587	1			T153	3		T154	13		T140	28
values[4]	800	1			T46	3		T139	13		T53	6
values[5]	680	1			T8	6		T139	3		T143	18
values[6]	2694	1			T13	5		T14	1		T15	10
values[7]	863	1			T17	9		T45	1		T139	7
values[8]	734	1			T9	6		T11	1		T17	15
values[9]	215	1			T35	1		T140	2		T182	10
minimum	14552	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

3926

1

T5

4

T8

1

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	5		T35	1		T153	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T44	2		T85	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T144	13		T161	7		T171	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T41	9		T253	13		T224	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	3		T148	1		T105	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T39	2		T142	1		T233	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T153	3		T154	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T140	14		T227	14		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T139	13		T53	4		T170	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T46	1		T160	1		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	5		T160	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T139	3		T143	7		T228	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1436	1			T13	1		T14	1		T15	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T35	1		T52	4		T159	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T17	3		T45	1		T139	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T228	15		T237	14		T41	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T17	5		T152	1		T236	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T9	4		T11	1		T85	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T35	1		T140	1		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T260	10		T289	14		T293	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14436	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T301	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T54	2		T256	6		T231	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T141	9		T144	14		T227	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T144	14		T161	7		T171	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T41	12		T253	11		T224	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T12	1		T105	9		T231	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T233	27		T236	14		T137	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T154	12		T145	12		T146	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T140	14		T227	14		T164	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T53	2		T232	16		T168	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T46	2		T187	14		T239	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	1		T160	11		T151	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T143	11		T228	6		T168	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T13	4		T16	1		T36	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T229	10		T149	6		T258	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T17	6		T140	3		T171	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T228	14		T237	11		T41	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T17	10		T236	2		T227	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	2		T141	10		T32	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T140	1		T182	9		T145	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T260	10		T289	5		T293	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T9	1		T21	4		T39	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T35	1		T140	1		T182	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T296	18		T290	19		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T299	2		T300	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T292	18		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T5	5		T35	1		T153	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T44	2		T85	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T161	7		T231	12		T245	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T41	9		T253	13		T204	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T148	1		T144	13		T171	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T39	2		T142	1		T233	25
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	3		T154	1		T145	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T140	14		T227	14		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T153	3		T148	1		T53	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T46	1		T160	1		T187	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T139	13		T160	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T228	7		T22	1		T90	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T8	5		T45	1		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T139	3		T143	7		T159	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1425	1			T13	1		T14	1		T15	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T35	1		T52	4		T41	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T17	5		T152	1		T139	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	398	1			T9	4		T11	1		T85	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T140	1		T182	9		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T290	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T299	1		T300	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T54	2		T256	6		T205	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T141	9		T144	14		T227	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T161	7		T231	11		T245	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T41	12		T253	11		T245	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T144	14		T171	2		T168	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T233	27		T236	14		T137	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	1		T154	12		T145	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T140	14		T227	14		T242	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T53	2		T146	4		T164	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T46	2		T187	14		T237	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T160	11		T151	11		T232	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T228	6		T90	2		T247	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	1		T187	4		T224	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T143	11		T229	10		T149	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T13	4		T16	1		T17	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T41	5		T155	14		T268	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T17	10		T140	3		T236	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T9	2		T141	10		T32	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	1		T35	1		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T44	2		T85	1		T141	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T144	15		T161	8		T171	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T41	13		T253	12		T224	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T12	3		T148	1		T105	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T39	2		T142	1		T233	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T153	1		T154	13		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T140	15		T227	15		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T139	1		T53	6		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T46	3		T160	1		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	5		T160	12		T151	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T139	1		T143	12		T228	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T13	5		T14	1		T15	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T35	1		T52	2		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T17	7		T45	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T228	15		T237	12		T41	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T17	11		T152	1		T236	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	4		T11	1		T85	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T35	1		T140	2		T182	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T260	11		T289	6		T293	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14551	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T301	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	4		T153	8		T54	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T144	13		T183	9		T227	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T144	12		T161	6		T171	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T41	8		T253	12		T224	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T12	1		T105	10		T231	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T233	23		T236	13		T137	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T153	2		T145	10		T146	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T140	13		T227	13		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T139	12		T170	14		T203	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T187	19		T296	11		T176	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T8	1		T224	9		T275	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T139	2		T143	6		T228	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1103	1			T15	9		T16	1		T37	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T52	2		T159	12		T258	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T17	2		T139	6		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T228	14		T237	13		T172	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T17	4		T236	11		T227	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	2		T56	9		T32	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T145	6		T102	10		T177	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T260	9		T289	13		T293	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T35	1		T140	2		T182	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T296	1		T290	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T299	2		T300	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T292	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T35	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T44	2		T85	1		T141	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T161	8		T231	13		T245	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T41	13		T253	12		T204	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T148	1		T144	15		T171	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T39	2		T142	1		T233	29
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	3		T154	13		T145	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T140	15		T227	15		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T153	1		T148	1		T53	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T46	3		T160	1		T187	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T139	1		T160	12		T151	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T228	7		T22	1		T90	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T8	5		T45	1		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T139	1		T143	12		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T13	5		T14	1		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T35	1		T52	2		T41	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T17	11		T152	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T9	4		T11	1		T85	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14544	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T296	17		T290	18		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T299	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T292	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	4		T153	8		T54	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T144	13		T183	9		T227	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T161	6		T231	10		T245	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T41	8		T253	12		T245	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T144	12		T171	4		T105	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T233	23		T236	13		T137	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	1		T145	10		T269	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T140	13		T227	13		T169	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T153	2		T170	14		T146	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T187	19		T237	6		T296	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T139	12		T254	1		T259	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T228	6		T90	2		T247	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	1		T187	5		T224	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T139	2		T143	6		T159	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1092	1			T15	9		T16	1		T17	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T52	2		T172	13		T155	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T17	4		T139	6		T153	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T9	2		T56	9		T32	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

3926

1

T5

4

T8

1

T9

2