Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23145

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17688

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

5457

1

T5

5

T9

6

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17415

1

T2

20

T3

20

T4

19

auto[1]

5730

1

T9

6

T11

1

T13

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19319

1

T2

20

T3

20

T4

19

auto[1]

3826

1

T8

1

T9

3

T12

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	181	1			T32	16		T153	9		T148	1
values[0]	47	1			T237	25		T41	21		T286	1
values[1]	690	1			T9	6		T85	1		T152	1
values[2]	848	1			T44	2		T46	3		T139	3
values[3]	788	1			T12	4		T141	11		T35	1
values[4]	626	1			T45	1		T85	1		T35	1
values[5]	678	1			T141	10		T148	1		T144	28
values[6]	707	1			T8	6		T11	1		T39	2
values[7]	664	1			T5	5		T35	1		T196	1
values[8]	445	1			T16	4		T233	18		T182	10
values[9]	2927	1			T13	5		T14	1		T15	10
minimum	14544	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	694	1			T9	6		T44	2		T46	3
values[1]	2798	1			T12	4		T13	5		T14	1
values[2]	715	1			T85	1		T141	11		T139	7
values[3]	664	1			T45	1		T35	1		T153	11
values[4]	825	1			T141	10		T148	1		T144	28
values[5]	627	1			T5	5		T8	6		T11	1
values[6]	577	1			T16	4		T35	1		T196	1
values[7]	514	1			T17	9		T142	1		T233	18
values[8]	813	1			T17	15		T32	16		T153	9
values[9]	86	1			T56	10		T153	3		T233	34
minimum	14832	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

3926

1

T5

4

T8

1

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T44	2		T85	1		T145	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T9	4		T46	1		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	3		T236	12		T227	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1464	1			T13	1		T14	1		T15	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T139	7		T140	4		T236	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T85	1		T141	1		T170	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T35	1		T144	13		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T45	1		T153	11		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T148	1		T144	14		T228	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T141	1		T183	10		T164	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	5		T148	1		T53	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	5		T11	1		T39	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T140	14		T159	13		T230	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T16	3		T35	1		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T149	1		T151	1		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T17	3		T142	1		T233	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T17	5		T153	9		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T32	5		T228	15		T54	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T153	3		T231	11		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T56	10		T233	15		T241	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14503	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T168	1		T155	18		T190	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T145	12		T165	5		T302	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	2		T46	2		T160	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	1		T236	2		T227	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1062	1			T13	4		T36	10		T201	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T140	3		T236	14		T256	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T141	10		T164	13		T171	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T144	14		T168	2		T260	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T227	14		T171	5		T158	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T144	14		T228	6		T137	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T141	9		T164	10		T105	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	1		T53	2		T149	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T269	15		T231	9		T165	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T140	14		T230	8		T102	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T16	1		T143	11		T102	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T149	9		T151	11		T182	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T17	6		T233	8		T231	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T17	10		T171	7		T253	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T32	11		T228	14		T54	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T231	11		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T233	19		T241	15		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	1		T21	4		T39	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T168	14		T155	18		T190	16

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T153	9		T148	1		T258	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T32	5		T161	7		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T237	14		T41	9		T286	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T85	1		T152	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	4		T145	7		T187	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T44	2		T236	12		T172	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T46	1		T139	3		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	3		T139	7		T236	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T141	1		T35	1		T170	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T35	1		T140	4		T144	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T45	1		T85	1		T153	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T148	1		T144	14		T228	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T141	1		T181	1		T164	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T8	5		T149	1		T187	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	1		T39	2		T139	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T140	14		T148	1		T159	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	5		T35	1		T196	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T182	1		T232	1		T224	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T16	3		T233	10		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T17	5		T153	3		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1464	1			T13	1		T14	1		T15	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14435	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T258	1		T231	11		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T32	11		T161	7		T242	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T237	11		T41	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T140	1		T145	12		T173	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	2		T145	4		T187	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T236	2		T243	2		T165	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T46	2		T154	12		T229	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	1		T236	14		T227	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T141	10		T164	13		T171	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T140	3		T144	14		T168	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T227	14		T171	5		T245	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T144	14		T228	6		T137	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T141	9		T164	10		T165	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	1		T149	6		T187	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T269	15		T105	13		T231	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T140	14		T53	2		T237	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T143	11		T102	5		T165	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T182	9		T232	4		T224	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T16	1		T233	8		T244	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T17	10		T149	9		T151	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1049	1			T13	4		T17	6		T36	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T21	4		T39	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T44	2		T85	1		T145	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T9	4		T46	3		T160	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	3		T236	3		T227	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1398	1			T13	5		T14	1		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T139	1		T140	4		T236	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T85	1		T141	11		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T35	1		T144	15		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T45	1		T153	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T148	1		T144	15		T228	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T141	10		T183	1		T164	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	5		T148	1		T53	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	1		T11	1		T39	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T140	15		T159	1		T230	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T16	3		T35	1		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T149	10		T151	12		T182	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T17	7		T142	1		T233	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T17	11		T153	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T32	12		T228	15		T54	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T153	1		T231	12		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T56	1		T233	20		T241	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14638	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T168	15		T155	19		T190	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T145	10		T172	12		T302	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T9	2		T145	6		T227	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T12	1		T236	11		T227	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1128	1			T15	9		T37	14		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T139	6		T140	3		T236	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T170	15		T164	12		T171	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T144	12		T145	2		T146	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T153	10		T227	13		T171	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T144	13		T228	6		T137	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T183	9		T164	12		T105	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	1		T187	5		T237	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	4		T139	12		T170	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T140	13		T159	12		T230	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T16	1		T143	6		T102	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T224	19		T172	13		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T17	2		T233	9		T231	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T17	4		T153	8		T171	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T32	4		T228	14		T54	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T153	2		T231	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T56	9		T233	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T237	13		T41	8		T173	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T155	17		T190	20		T280	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T153	1		T148	1		T258	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T32	12		T161	8		T242	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T237	12		T41	13		T286	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T85	1		T152	1		T140	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	4		T145	5		T187	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T44	2		T236	3		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T46	3		T139	1		T154	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	3		T139	1		T236	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T141	11		T35	1		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T35	1		T140	4		T144	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	1		T85	1		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T148	1		T144	15		T228	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T141	10		T181	1		T164	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T8	5		T149	7		T187	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	1		T39	2		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T140	15		T148	1		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	1		T35	1		T196	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T182	10		T232	5		T224	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T16	3		T233	9		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T17	11		T153	1		T149	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1392	1			T13	5		T14	1		T15	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14544	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T153	8		T258	1		T231	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T32	4		T161	6		T105	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T237	13		T41	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T145	10		T173	9		T303	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	2		T145	6		T187	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T236	11		T172	12		T243	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T139	2		T52	2		T159	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	1		T139	6		T236	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T170	15		T164	12		T171	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T140	3		T144	12		T145	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T153	10		T227	13		T171	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T144	13		T228	6		T137	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T164	12		T90	2		T259	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	1		T187	5		T248	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T139	12		T183	9		T269	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T140	13		T159	12		T237	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	4		T143	6		T170	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T224	19		T42	2		T247	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T16	1		T233	9		T251	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T17	4		T153	2		T171	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1121	1			T15	9		T17	2		T56	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19219

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

3926

1

T5

4

T8

1

T9

2