Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5493	1			T2	20		T3	20		T4	3
testmodes[AdcCtrlTestmodeNormal]	4649	1			T4	10		T5	11		T6	6
testmodes[AdcCtrlTestmodeLowpower]	4714	1			T7	13		T8	4		T11	16
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2790	1			T2	19		T3	19		T5	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1408	1			T4	3		T5	5		T6	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1177	1			T16	3		T58	14		T55	12
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1450	1			T4	3		T5	4		T6	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1691	1			T4	6		T5	6		T6	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1179	1			T13	1		T16	2		T17	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1136	1			T58	20		T55	18		T56	11
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1217	1			T13	2		T16	4		T17	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2109	1			T7	12		T8	3		T11	15