Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.78 99.07 96.67 100.00 100.00 98.82 98.33 91.54


Total tests in report: 920
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
74.18 74.18 97.61 97.61 82.83 82.83 87.91 87.91 54.05 54.05 96.15 96.15 89.15 89.15 11.58 11.58 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1348795866
78.94 4.75 98.20 0.59 83.99 1.15 94.67 6.75 75.68 21.62 96.96 0.81 90.15 1.00 12.93 1.35 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.95329295
82.08 3.14 98.39 0.19 91.11 7.12 94.67 0.00 75.68 0.00 97.39 0.43 93.66 3.51 23.68 10.76 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.403876494
84.54 2.46 98.39 0.00 91.15 0.04 94.67 0.00 91.89 16.22 97.45 0.06 93.66 0.00 24.61 0.92 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.2776475148
86.26 1.72 98.88 0.50 94.15 3.01 96.68 2.01 91.89 0.00 98.57 1.12 95.33 1.67 28.33 3.72 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.2816056199
87.47 1.21 98.88 0.00 94.15 0.00 96.68 0.00 91.89 0.00 98.57 0.00 95.66 0.33 36.44 8.11 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.3360669066
88.51 1.04 98.88 0.00 94.15 0.00 96.68 0.00 91.89 0.00 98.57 0.00 95.66 0.00 43.75 7.31 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.3654152234
89.42 0.91 98.88 0.00 94.15 0.00 96.68 0.00 91.89 0.00 98.57 0.00 95.66 0.00 50.09 6.34 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.1566986655
90.24 0.82 98.88 0.00 94.15 0.00 96.68 0.00 97.30 5.41 98.57 0.00 95.66 0.00 50.44 0.35 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.3343748651
90.92 0.68 98.88 0.00 94.24 0.08 96.92 0.24 100.00 2.70 98.57 0.00 95.66 0.00 52.16 1.72 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1260232341
91.55 0.63 98.88 0.00 94.24 0.00 96.92 0.00 100.00 0.00 98.57 0.00 95.66 0.00 56.55 4.39 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.3958550614
92.09 0.54 98.88 0.00 94.24 0.00 96.92 0.00 100.00 0.00 98.57 0.00 95.66 0.00 60.34 3.79 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.891892447
92.55 0.46 98.88 0.00 94.24 0.00 96.92 0.00 100.00 0.00 98.57 0.00 95.66 0.00 63.59 3.24 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.2062994201
93.01 0.46 98.88 0.00 95.68 1.44 97.39 0.47 100.00 0.00 98.63 0.06 96.33 0.67 64.14 0.55 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1899968523
93.42 0.41 98.92 0.03 95.80 0.12 99.76 2.37 100.00 0.00 98.70 0.06 96.49 0.17 64.29 0.15 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.475441067
93.80 0.38 98.92 0.00 95.80 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.49 0.00 66.96 2.67 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.2558637720
94.18 0.37 98.92 0.00 95.80 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.49 0.00 69.58 2.62 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1034189639
94.51 0.33 98.92 0.00 95.80 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.49 0.00 71.87 2.30 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3179522301
94.79 0.29 98.92 0.00 95.80 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.49 0.00 73.87 2.00 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.2349694353
95.03 0.24 98.92 0.00 95.80 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.49 0.00 75.52 1.65 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.2655033924
95.26 0.23 98.98 0.06 96.05 0.25 99.76 0.00 100.00 0.00 98.82 0.12 97.66 1.17 75.52 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4198512351
95.46 0.20 98.98 0.00 96.05 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.66 0.00 76.92 1.40 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.2305618412
95.64 0.19 98.98 0.00 96.05 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.17 78.06 1.15 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.2853981346
95.80 0.15 98.98 0.00 96.05 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 79.14 1.07 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.1665349100
95.93 0.13 98.98 0.00 96.05 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 80.06 0.92 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.3655973461
96.05 0.12 98.98 0.00 96.05 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 80.93 0.87 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.2812829941
96.17 0.11 98.98 0.00 96.05 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 81.73 0.80 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.474682087
96.28 0.11 98.98 0.00 96.05 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 82.51 0.77 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.1026739506
96.37 0.09 98.98 0.00 96.05 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 83.13 0.62 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3940426565
96.44 0.07 98.98 0.00 96.05 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 83.65 0.52 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.3078170530
96.51 0.07 98.98 0.00 96.05 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 84.15 0.50 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_clock_gating.2589938647
96.58 0.07 98.98 0.00 96.05 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.00 0.17 84.48 0.32 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.1967364930
96.65 0.07 98.98 0.00 96.34 0.29 99.76 0.00 100.00 0.00 98.82 0.00 98.00 0.00 84.65 0.17 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.741664484
96.71 0.06 99.07 0.09 96.46 0.12 100.00 0.24 100.00 0.00 98.82 0.00 98.00 0.00 84.65 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.2015835003
96.78 0.06 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.00 0.00 85.10 0.45 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.4209351053
96.84 0.06 99.07 0.00 96.46 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.00 0.00 85.53 0.42 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1038984486
96.89 0.05 99.07 0.00 96.67 0.21 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.17 85.53 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.3576500012
96.94 0.05 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 85.87 0.35 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.2540664816
96.99 0.05 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 86.20 0.32 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_both.3669538988
97.03 0.05 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 86.52 0.32 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all.3944877147
97.08 0.04 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 86.82 0.30 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.2030528111
97.12 0.04 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 87.10 0.27 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.3368959785
97.15 0.04 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 87.35 0.25 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.3990458069
97.19 0.04 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 87.60 0.25 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.3245952556
97.22 0.03 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 87.82 0.22 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.3372975573
97.25 0.03 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 88.05 0.22 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.3838627031
97.28 0.03 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 88.27 0.22 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.3107309473
97.31 0.03 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 88.47 0.20 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.2936253891
97.34 0.03 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 88.67 0.20 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.561667105
97.37 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 88.84 0.17 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt.1003227145
97.39 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.17 88.84 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.741434059
97.41 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.99 0.15 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.723115280
97.43 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.14 0.15 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3426907203
97.45 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.29 0.15 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.2023670900
97.47 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.42 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.406045539
97.49 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.54 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.1291806265
97.51 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.67 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.1314447183
97.53 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.79 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.1272121717
97.54 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.92 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.4290343939
97.56 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.02 0.10 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.2026500017
97.57 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.12 0.10 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.524403780
97.59 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.22 0.10 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.3031994008
97.60 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.29 0.07 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2586669252
97.61 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.37 0.07 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.2534403075
97.62 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.44 0.07 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.3095065015
97.63 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.52 0.07 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3967236688
97.64 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.59 0.07 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup.4069117738
97.65 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.64 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.151313398
97.65 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.69 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.2070274901
97.66 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.74 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.103082370
97.67 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.79 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.1137407254
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.84 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.3468915809
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.89 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.3348574943
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.94 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.3926768317
97.70 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.99 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.1915668551
97.70 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.04 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all.3115810103
97.71 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.09 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_fsm_reset.2485942238
97.72 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.14 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.1807200448
97.73 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.19 0.05 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.2363501005
97.73 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.22 0.02 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.723983724
97.73 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.24 0.02 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.4276935096
97.74 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.27 0.02 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.133161735
97.74 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.29 0.02 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.2527727513
97.74 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.32 0.02 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.2271105125
97.75 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.34 0.02 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.164788299
97.75 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.37 0.02 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_fsm_reset.3602107728
97.75 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.39 0.02 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.2536281102
97.76 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.42 0.02 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.156239943
97.76 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.44 0.02 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_fsm_reset.916755129
97.76 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.46 0.02 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.1620171170
97.77 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.49 0.02 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt.3187875674
97.77 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.51 0.02 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.3654210500
97.78 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 91.54 0.02 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.2223799298

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.591357807
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2490190698
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1973646057
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2389644823
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.4036073032
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.516327234
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3650933454
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.754874200
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.672053626
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2159872530
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1521520438
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.3877182227
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1811316524
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2810751614
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2080172293
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2778432901
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2258189363
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.776189994
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2163118913
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.311433659
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2065621854
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.539599119
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1289847563
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.3651604557
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.119948989
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.371781165
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1578462283
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3736726744
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1875150720
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.3986510587
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3606026347
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1141393299
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2359879876
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2193485340
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1789682461
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2686048878
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2852407652
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1980398921
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2302558758
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.178326696
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2800225272
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2741506940
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1121690896
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1576407238
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2991567814
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.4153816607
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.261259883
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.2501384302
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3110661059
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.485819288
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1159908112
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1678885637
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1375465390
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.4287328448
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.267392183
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3679664291
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.262422485
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.565503292
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.512812641
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.455647981
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4078745714
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.885329105
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2677240825
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3063740696
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2838525584
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.293628069
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1322885822
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.128764448
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3298916611
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.377294710
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1249368621
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2027953952
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1006325693
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3117506481
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.496988746
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.273973649
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4179699421
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.678841275
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.82143998
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.519869028
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.1977809137
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3608175207
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3278924715
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.1897756775
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.716360925
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.4181088913
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.4088075477
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.1191987720
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.3998012516
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.4186508448
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.2238493502
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.1491133455
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.79464739
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3789100495
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1320297061
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2122071343
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4107624736
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.733369639
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.1305168053
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3963574670
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.653279469
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1162043982
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.516785888
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.1522431239
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.179803950
/workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.3642995100
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Total test records in report: 920
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.2015835003 Sep 24 06:58:02 AM UTC 24 Sep 24 06:58:06 AM UTC 24 506586650 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.283090143 Sep 24 06:58:02 AM UTC 24 Sep 24 06:58:10 AM UTC 24 6078939877 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.3576500012 Sep 24 06:57:44 AM UTC 24 Sep 24 06:58:14 AM UTC 24 5608858887 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.984603109 Sep 24 06:58:01 AM UTC 24 Sep 24 06:58:17 AM UTC 24 7711323727 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.1709234816 Sep 24 06:58:12 AM UTC 24 Sep 24 06:58:24 AM UTC 24 3625129143 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.4100883883 Sep 24 06:57:55 AM UTC 24 Sep 24 06:58:24 AM UTC 24 5603799702 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.95329295 Sep 24 06:58:18 AM UTC 24 Sep 24 06:58:25 AM UTC 24 4157886818 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.1913894942 Sep 24 06:57:58 AM UTC 24 Sep 24 06:58:26 AM UTC 24 28294947944 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.3557571678 Sep 24 06:58:22 AM UTC 24 Sep 24 06:58:27 AM UTC 24 464716552 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1348795866 Sep 24 06:57:59 AM UTC 24 Sep 24 06:58:38 AM UTC 24 192144008170 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.3120812907 Sep 24 06:58:19 AM UTC 24 Sep 24 06:58:38 AM UTC 24 4391709566 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.3037692540 Sep 24 06:58:37 AM UTC 24 Sep 24 06:58:40 AM UTC 24 402987902 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.170350210 Sep 24 06:58:32 AM UTC 24 Sep 24 06:58:42 AM UTC 24 1460563587 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.3679412402 Sep 24 06:58:23 AM UTC 24 Sep 24 06:58:42 AM UTC 24 6015799262 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.1483030626 Sep 24 06:58:14 AM UTC 24 Sep 24 06:58:43 AM UTC 24 35615135624 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.4148911194 Sep 24 06:58:28 AM UTC 24 Sep 24 06:58:47 AM UTC 24 4161070733 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.191537798 Sep 24 06:58:38 AM UTC 24 Sep 24 06:58:52 AM UTC 24 5902557088 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.2901077698 Sep 24 06:58:48 AM UTC 24 Sep 24 06:58:54 AM UTC 24 3848482293 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1260232341 Sep 24 06:58:17 AM UTC 24 Sep 24 06:58:54 AM UTC 24 50820246432 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.3812438562 Sep 24 06:58:57 AM UTC 24 Sep 24 06:58:59 AM UTC 24 547547431 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.475441067 Sep 24 06:58:37 AM UTC 24 Sep 24 06:58:59 AM UTC 24 7926236898 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.2925403378 Sep 24 06:58:57 AM UTC 24 Sep 24 06:59:07 AM UTC 24 5596298243 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.2583989497 Sep 24 06:58:55 AM UTC 24 Sep 24 06:59:07 AM UTC 24 7874930720 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.951747784 Sep 24 06:58:51 AM UTC 24 Sep 24 06:59:25 AM UTC 24 27703559755 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.153206781 Sep 24 06:59:30 AM UTC 24 Sep 24 06:59:48 AM UTC 24 3784808460 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.723983724 Sep 24 06:57:55 AM UTC 24 Sep 24 06:59:54 AM UTC 24 168276115219 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.3877576599 Sep 24 06:59:00 AM UTC 24 Sep 24 06:59:55 AM UTC 24 168098939983 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1054374055 Sep 24 06:58:53 AM UTC 24 Sep 24 06:59:56 AM UTC 24 50881917182 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2810579121 Sep 24 06:59:49 AM UTC 24 Sep 24 06:59:57 AM UTC 24 7019331354 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.3630938404 Sep 24 06:57:44 AM UTC 24 Sep 24 06:59:59 AM UTC 24 171747960386 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.1305855302 Sep 24 06:59:57 AM UTC 24 Sep 24 06:59:59 AM UTC 24 532376448 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.1180618143 Sep 24 06:59:32 AM UTC 24 Sep 24 07:00:05 AM UTC 24 27754060323 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1034189639 Sep 24 06:58:03 AM UTC 24 Sep 24 07:00:05 AM UTC 24 163053114364 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.1715574442 Sep 24 06:59:56 AM UTC 24 Sep 24 07:00:06 AM UTC 24 7936752176 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.1109158485 Sep 24 06:58:28 AM UTC 24 Sep 24 07:00:12 AM UTC 24 36593024886 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.1489366625 Sep 24 06:59:58 AM UTC 24 Sep 24 07:00:20 AM UTC 24 6088685556 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.2078451678 Sep 24 07:00:21 AM UTC 24 Sep 24 07:00:26 AM UTC 24 3711133766 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3006354570 Sep 24 07:00:26 AM UTC 24 Sep 24 07:00:34 AM UTC 24 2457563747 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.87214888 Sep 24 07:00:21 AM UTC 24 Sep 24 07:00:37 AM UTC 24 24896119190 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.3473837257 Sep 24 07:00:34 AM UTC 24 Sep 24 07:00:37 AM UTC 24 448241198 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.2704176829 Sep 24 06:58:01 AM UTC 24 Sep 24 07:00:39 AM UTC 24 172235011892 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1224566920 Sep 24 06:58:25 AM UTC 24 Sep 24 07:00:58 AM UTC 24 167079310787 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.2816056199 Sep 24 06:58:48 AM UTC 24 Sep 24 07:01:00 AM UTC 24 183396473410 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.3890532448 Sep 24 07:00:36 AM UTC 24 Sep 24 07:01:04 AM UTC 24 5919613788 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.1223018475 Sep 24 07:01:04 AM UTC 24 Sep 24 07:01:16 AM UTC 24 5339585281 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.1368749766 Sep 24 06:57:48 AM UTC 24 Sep 24 07:01:24 AM UTC 24 165155652095 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3648930437 Sep 24 07:01:25 AM UTC 24 Sep 24 07:01:33 AM UTC 24 15278249068 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.403876494 Sep 24 06:58:07 AM UTC 24 Sep 24 07:01:43 AM UTC 24 367705089099 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.3583208936 Sep 24 06:58:38 AM UTC 24 Sep 24 07:01:48 AM UTC 24 161585354358 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.436994302 Sep 24 07:01:45 AM UTC 24 Sep 24 07:01:48 AM UTC 24 398581203 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.1272740074 Sep 24 06:58:03 AM UTC 24 Sep 24 07:01:55 AM UTC 24 326385484356 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.3647798665 Sep 24 07:00:00 AM UTC 24 Sep 24 07:02:03 AM UTC 24 160469168842 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.913220172 Sep 24 07:01:12 AM UTC 24 Sep 24 07:02:08 AM UTC 24 25342349610 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.1589611670 Sep 24 07:01:46 AM UTC 24 Sep 24 07:02:13 AM UTC 24 5931872990 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.2912568949 Sep 24 06:59:00 AM UTC 24 Sep 24 07:02:25 AM UTC 24 323410486382 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.638829618 Sep 24 06:58:03 AM UTC 24 Sep 24 07:02:29 AM UTC 24 330829619400 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.1151770516 Sep 24 07:00:08 AM UTC 24 Sep 24 07:02:43 AM UTC 24 174715752017 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.822171989 Sep 24 07:02:44 AM UTC 24 Sep 24 07:02:47 AM UTC 24 4400257776 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.1072166576 Sep 24 06:58:27 AM UTC 24 Sep 24 07:02:52 AM UTC 24 339730405278 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.4182137445 Sep 24 06:57:59 AM UTC 24 Sep 24 07:03:08 AM UTC 24 70699077006 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.2543700448 Sep 24 06:58:40 AM UTC 24 Sep 24 07:03:17 AM UTC 24 331577805073 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.2376846586 Sep 24 06:58:27 AM UTC 24 Sep 24 07:03:17 AM UTC 24 189636823024 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.3031292970 Sep 24 07:03:18 AM UTC 24 Sep 24 07:03:21 AM UTC 24 381931782 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.140275658 Sep 24 07:02:48 AM UTC 24 Sep 24 07:03:22 AM UTC 24 35852456888 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.2855542879 Sep 24 06:58:25 AM UTC 24 Sep 24 07:03:31 AM UTC 24 485867943302 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.302982125 Sep 24 07:03:08 AM UTC 24 Sep 24 07:03:37 AM UTC 24 60899093550 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.3026422456 Sep 24 07:03:21 AM UTC 24 Sep 24 07:03:37 AM UTC 24 5947254599 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.3644113852 Sep 24 07:00:00 AM UTC 24 Sep 24 07:03:45 AM UTC 24 495164227991 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.4018925769 Sep 24 06:58:54 AM UTC 24 Sep 24 07:04:11 AM UTC 24 175312020799 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.4190917059 Sep 24 07:02:09 AM UTC 24 Sep 24 07:04:12 AM UTC 24 411502156600 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3865596652 Sep 24 07:00:58 AM UTC 24 Sep 24 07:04:17 AM UTC 24 391318304817 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.3525605240 Sep 24 06:59:21 AM UTC 24 Sep 24 07:04:36 AM UTC 24 166335000923 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.4199491424 Sep 24 07:04:37 AM UTC 24 Sep 24 07:04:41 AM UTC 24 4498514249 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.167445202 Sep 24 07:01:00 AM UTC 24 Sep 24 07:04:48 AM UTC 24 332923982994 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2018878304 Sep 24 06:58:43 AM UTC 24 Sep 24 07:04:52 AM UTC 24 155210949085 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.12990807 Sep 24 06:59:55 AM UTC 24 Sep 24 07:04:52 AM UTC 24 76996423149 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3417266451 Sep 24 07:00:01 AM UTC 24 Sep 24 07:04:52 AM UTC 24 338128414920 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.2376419571 Sep 24 06:58:25 AM UTC 24 Sep 24 07:04:55 AM UTC 24 483650929622 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.12371239 Sep 24 07:04:53 AM UTC 24 Sep 24 07:04:57 AM UTC 24 501760951 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3829976456 Sep 24 07:04:52 AM UTC 24 Sep 24 07:05:00 AM UTC 24 1450851939 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.170439314 Sep 24 07:04:56 AM UTC 24 Sep 24 07:05:01 AM UTC 24 5894854372 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.1796135102 Sep 24 07:01:48 AM UTC 24 Sep 24 07:05:23 AM UTC 24 162237020462 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.1876884738 Sep 24 06:59:35 AM UTC 24 Sep 24 07:05:24 AM UTC 24 75627613027 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.1894545313 Sep 24 06:58:25 AM UTC 24 Sep 24 07:05:30 AM UTC 24 165203546049 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2032882178 Sep 24 07:02:04 AM UTC 24 Sep 24 07:05:36 AM UTC 24 325024776613 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.3195372807 Sep 24 07:03:38 AM UTC 24 Sep 24 07:05:38 AM UTC 24 163355454118 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.945052874 Sep 24 07:01:56 AM UTC 24 Sep 24 07:05:42 AM UTC 24 322475209465 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.1042881359 Sep 24 07:05:43 AM UTC 24 Sep 24 07:05:50 AM UTC 24 4825194297 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.3619878710 Sep 24 07:03:46 AM UTC 24 Sep 24 07:05:56 AM UTC 24 164212531056 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.2776475148 Sep 24 06:58:53 AM UTC 24 Sep 24 07:06:08 AM UTC 24 102469781287 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.3949566679 Sep 24 06:57:45 AM UTC 24 Sep 24 07:06:09 AM UTC 24 321611579129 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.3951494375 Sep 24 07:04:41 AM UTC 24 Sep 24 07:06:15 AM UTC 24 38242904981 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.972146016 Sep 24 07:06:09 AM UTC 24 Sep 24 07:06:16 AM UTC 24 625307760 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.2713601818 Sep 24 07:06:17 AM UTC 24 Sep 24 07:06:19 AM UTC 24 583678549 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.3135293276 Sep 24 07:05:51 AM UTC 24 Sep 24 07:06:19 AM UTC 24 35462364966 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.4121997205 Sep 24 07:00:25 AM UTC 24 Sep 24 07:06:21 AM UTC 24 75374620052 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.3027372579 Sep 24 07:00:39 AM UTC 24 Sep 24 07:06:22 AM UTC 24 492489832286 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.2476915293 Sep 24 07:00:38 AM UTC 24 Sep 24 07:06:25 AM UTC 24 487785280004 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.1598372012 Sep 24 07:06:17 AM UTC 24 Sep 24 07:06:26 AM UTC 24 6018863348 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.3251496840 Sep 24 06:59:13 AM UTC 24 Sep 24 07:07:07 AM UTC 24 173548893983 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.731507103 Sep 24 06:58:28 AM UTC 24 Sep 24 07:07:17 AM UTC 24 131175702939 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.2853981346 Sep 24 07:00:40 AM UTC 24 Sep 24 07:07:25 AM UTC 24 485775644865 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.2186195891 Sep 24 07:07:27 AM UTC 24 Sep 24 07:07:30 AM UTC 24 2861026897 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.4159230835 Sep 24 06:59:58 AM UTC 24 Sep 24 07:07:36 AM UTC 24 156796334632 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.3360669066 Sep 24 07:01:04 AM UTC 24 Sep 24 07:07:38 AM UTC 24 501656315225 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.3490045758 Sep 24 07:00:34 AM UTC 24 Sep 24 07:07:40 AM UTC 24 119267962808 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.2357032266 Sep 24 07:05:02 AM UTC 24 Sep 24 07:07:45 AM UTC 24 158867906327 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.406045539 Sep 24 07:07:40 AM UTC 24 Sep 24 07:07:47 AM UTC 24 9409935643 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.2609822827 Sep 24 07:07:45 AM UTC 24 Sep 24 07:07:48 AM UTC 24 547674933 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.902080841 Sep 24 07:07:31 AM UTC 24 Sep 24 07:07:51 AM UTC 24 44679991144 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2418756533 Sep 24 07:00:42 AM UTC 24 Sep 24 07:07:52 AM UTC 24 485057619489 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.65044768 Sep 24 07:07:49 AM UTC 24 Sep 24 07:08:05 AM UTC 24 5681227263 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.2108499878 Sep 24 07:05:02 AM UTC 24 Sep 24 07:08:14 AM UTC 24 327596830802 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.2062994201 Sep 24 06:58:25 AM UTC 24 Sep 24 07:08:22 AM UTC 24 555061212174 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.1665349100 Sep 24 07:00:55 AM UTC 24 Sep 24 07:08:23 AM UTC 24 542354073278 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.2991863380 Sep 24 07:06:20 AM UTC 24 Sep 24 07:08:25 AM UTC 24 162771454325 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.208717507 Sep 24 07:08:26 AM UTC 24 Sep 24 07:08:31 AM UTC 24 3404087765 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4270415447 Sep 24 07:06:23 AM UTC 24 Sep 24 07:08:37 AM UTC 24 165562536646 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.3838627031 Sep 24 07:07:08 AM UTC 24 Sep 24 07:08:43 AM UTC 24 535144763289 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2494054050 Sep 24 07:08:43 AM UTC 24 Sep 24 07:09:00 AM UTC 24 10371130387 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.297856788 Sep 24 06:58:15 AM UTC 24 Sep 24 07:09:03 AM UTC 24 94438116454 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.4183023772 Sep 24 07:09:03 AM UTC 24 Sep 24 07:09:06 AM UTC 24 471106291 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1236156561 Sep 24 06:59:20 AM UTC 24 Sep 24 07:09:23 AM UTC 24 189931209783 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.3343748651 Sep 24 07:01:17 AM UTC 24 Sep 24 07:09:26 AM UTC 24 111206821951 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.1743732947 Sep 24 07:09:06 AM UTC 24 Sep 24 07:09:34 AM UTC 24 5871462491 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.3958550614 Sep 24 07:03:17 AM UTC 24 Sep 24 07:09:43 AM UTC 24 500004858954 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.3896555324 Sep 24 07:01:49 AM UTC 24 Sep 24 07:09:44 AM UTC 24 331099135511 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.1835358385 Sep 24 06:58:44 AM UTC 24 Sep 24 07:09:48 AM UTC 24 173467486055 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.2032996213 Sep 24 07:02:52 AM UTC 24 Sep 24 07:09:50 AM UTC 24 108244612475 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.351406264 Sep 24 07:04:13 AM UTC 24 Sep 24 07:10:02 AM UTC 24 495298539882 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3854732178 Sep 24 07:05:24 AM UTC 24 Sep 24 07:10:03 AM UTC 24 325551394752 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.2066982247 Sep 24 07:00:06 AM UTC 24 Sep 24 07:10:04 AM UTC 24 339388995870 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.2305618412 Sep 24 07:06:10 AM UTC 24 Sep 24 07:10:15 AM UTC 24 383106039588 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.3450507308 Sep 24 07:10:04 AM UTC 24 Sep 24 07:10:24 AM UTC 24 4608015324 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.571982881 Sep 24 06:59:08 AM UTC 24 Sep 24 07:10:28 AM UTC 24 489990304751 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.2788222716 Sep 24 07:08:32 AM UTC 24 Sep 24 07:10:38 AM UTC 24 34655364491 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.4082124287 Sep 24 07:10:39 AM UTC 24 Sep 24 07:10:42 AM UTC 24 442790277 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.3671574615 Sep 24 07:06:20 AM UTC 24 Sep 24 07:10:49 AM UTC 24 163994716155 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.943566023 Sep 24 07:10:43 AM UTC 24 Sep 24 07:10:59 AM UTC 24 5741827188 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3940426565 Sep 24 07:10:25 AM UTC 24 Sep 24 07:11:00 AM UTC 24 125346630028 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.76801041 Sep 24 07:10:05 AM UTC 24 Sep 24 07:11:01 AM UTC 24 26393194320 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.891892447 Sep 24 06:58:46 AM UTC 24 Sep 24 07:11:12 AM UTC 24 531559009958 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.3614015128 Sep 24 06:58:35 AM UTC 24 Sep 24 07:11:29 AM UTC 24 104499394918 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.2033742958 Sep 24 07:06:26 AM UTC 24 Sep 24 07:11:29 AM UTC 24 165442614639 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.527149554 Sep 24 07:03:24 AM UTC 24 Sep 24 07:11:31 AM UTC 24 159903655119 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.3245194949 Sep 24 07:03:33 AM UTC 24 Sep 24 07:11:40 AM UTC 24 324395142623 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.2542398551 Sep 24 07:02:30 AM UTC 24 Sep 24 07:11:48 AM UTC 24 177990531757 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3846558009 Sep 24 07:02:14 AM UTC 24 Sep 24 07:11:49 AM UTC 24 595496166357 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.4044263415 Sep 24 07:11:41 AM UTC 24 Sep 24 07:11:54 AM UTC 24 4724541588 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1110571462 Sep 24 06:58:25 AM UTC 24 Sep 24 07:12:20 AM UTC 24 401577329695 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.4286326434 Sep 24 07:05:25 AM UTC 24 Sep 24 07:12:21 AM UTC 24 185748954098 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.4209351053 Sep 24 07:08:06 AM UTC 24 Sep 24 07:12:23 AM UTC 24 538512255280 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.211797979 Sep 24 07:12:21 AM UTC 24 Sep 24 07:12:24 AM UTC 24 539397277 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.474682087 Sep 24 07:02:26 AM UTC 24 Sep 24 07:12:35 AM UTC 24 357008336475 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.2615234750 Sep 24 07:12:24 AM UTC 24 Sep 24 07:12:40 AM UTC 24 6041986172 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2941093457 Sep 24 07:11:54 AM UTC 24 Sep 24 07:12:38 AM UTC 24 10572610809 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2849136727 Sep 24 07:07:52 AM UTC 24 Sep 24 07:12:45 AM UTC 24 165042681782 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.1811092660 Sep 24 07:11:49 AM UTC 24 Sep 24 07:12:50 AM UTC 24 26567677189 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.3823647754 Sep 24 07:05:56 AM UTC 24 Sep 24 07:12:51 AM UTC 24 111236624875 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.461886992 Sep 24 07:05:31 AM UTC 24 Sep 24 07:12:58 AM UTC 24 584854435472 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.3654152234 Sep 24 07:08:24 AM UTC 24 Sep 24 07:13:04 AM UTC 24 531154678559 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.2527727513 Sep 24 07:11:13 AM UTC 24 Sep 24 07:13:05 AM UTC 24 185725501087 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.4075758443 Sep 24 07:13:05 AM UTC 24 Sep 24 07:13:13 AM UTC 24 26527671834 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.1876289842 Sep 24 07:13:05 AM UTC 24 Sep 24 07:13:16 AM UTC 24 3248797515 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.1431543033 Sep 24 07:07:49 AM UTC 24 Sep 24 07:13:20 AM UTC 24 335129830446 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.151313398 Sep 24 07:07:37 AM UTC 24 Sep 24 07:13:22 AM UTC 24 83343127943 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.365968356 Sep 24 07:13:22 AM UTC 24 Sep 24 07:13:25 AM UTC 24 543305707 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3701915106 Sep 24 07:13:17 AM UTC 24 Sep 24 07:13:31 AM UTC 24 5178640173 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.2026500017 Sep 24 07:11:31 AM UTC 24 Sep 24 07:13:34 AM UTC 24 164373484064 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.1718711003 Sep 24 07:13:25 AM UTC 24 Sep 24 07:13:40 AM UTC 24 5962481882 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3426907203 Sep 24 07:09:49 AM UTC 24 Sep 24 07:13:51 AM UTC 24 405244455472 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.1418644390 Sep 24 07:06:22 AM UTC 24 Sep 24 07:14:03 AM UTC 24 162670300062 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.2032026933 Sep 24 06:59:08 AM UTC 24 Sep 24 07:14:12 AM UTC 24 323249891008 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.837178300 Sep 24 07:07:19 AM UTC 24 Sep 24 07:14:26 AM UTC 24 165763002172 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.2655033924 Sep 24 07:08:23 AM UTC 24 Sep 24 07:14:36 AM UTC 24 589921777365 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.3639185649 Sep 24 07:10:03 AM UTC 24 Sep 24 07:14:38 AM UTC 24 374126978967 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.2667286314 Sep 24 07:14:39 AM UTC 24 Sep 24 07:14:58 AM UTC 24 3721925381 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1262383572 Sep 24 07:09:44 AM UTC 24 Sep 24 07:15:24 AM UTC 24 334607605248 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.3331277115 Sep 24 07:13:35 AM UTC 24 Sep 24 07:15:31 AM UTC 24 163175770277 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.3870820881 Sep 24 07:09:45 AM UTC 24 Sep 24 07:15:35 AM UTC 24 381870970592 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.103082370 Sep 24 07:15:31 AM UTC 24 Sep 24 07:15:41 AM UTC 24 2600447541 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.274661532 Sep 24 07:15:42 AM UTC 24 Sep 24 07:15:44 AM UTC 24 469766601 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.1566986655 Sep 24 06:57:54 AM UTC 24 Sep 24 07:15:58 AM UTC 24 497002000682 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.957291240 Sep 24 07:14:58 AM UTC 24 Sep 24 07:16:00 AM UTC 24 46117619537 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.747437730 Sep 24 07:15:45 AM UTC 24 Sep 24 07:16:14 AM UTC 24 6075168243 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.2979479784 Sep 24 07:12:59 AM UTC 24 Sep 24 07:16:16 AM UTC 24 197848408620 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.4168782405 Sep 24 07:16:01 AM UTC 24 Sep 24 07:16:50 AM UTC 24 166253059675 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.4244619340 Sep 24 07:07:51 AM UTC 24 Sep 24 07:17:04 AM UTC 24 170605046468 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1273091980 Sep 24 07:06:27 AM UTC 24 Sep 24 07:17:09 AM UTC 24 197352266315 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.2740880463 Sep 24 07:09:35 AM UTC 24 Sep 24 07:17:42 AM UTC 24 489111041672 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.75629823 Sep 24 07:14:13 AM UTC 24 Sep 24 07:17:47 AM UTC 24 197988754920 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2119830407 Sep 24 07:11:02 AM UTC 24 Sep 24 07:17:54 AM UTC 24 163744342440 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.1624390340 Sep 24 07:17:48 AM UTC 24 Sep 24 07:17:57 AM UTC 24 3027945041 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.1144069743 Sep 24 06:59:26 AM UTC 24 Sep 24 07:18:16 AM UTC 24 341931760329 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.2534403075 Sep 24 07:13:42 AM UTC 24 Sep 24 07:18:27 AM UTC 24 162968700670 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.316728047 Sep 24 07:18:17 AM UTC 24 Sep 24 07:18:37 AM UTC 24 4469971467 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.2829223832 Sep 24 07:00:13 AM UTC 24 Sep 24 07:18:39 AM UTC 24 397956084272 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.2127815119 Sep 24 07:18:38 AM UTC 24 Sep 24 07:18:41 AM UTC 24 426788984 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2196155041 Sep 24 06:57:46 AM UTC 24 Sep 24 07:18:43 AM UTC 24 493544022534 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.3090771319 Sep 24 07:15:35 AM UTC 24 Sep 24 07:18:43 AM UTC 24 187487560262 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.2599975845 Sep 24 07:10:16 AM UTC 24 Sep 24 07:18:54 AM UTC 24 99026201522 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.723115280 Sep 24 07:07:41 AM UTC 24 Sep 24 07:18:54 AM UTC 24 280463721018 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.2469136210 Sep 24 07:18:40 AM UTC 24 Sep 24 07:18:57 AM UTC 24 5802103783 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.985459109 Sep 24 07:13:14 AM UTC 24 Sep 24 07:19:11 AM UTC 24 92371150599 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.2716304357 Sep 24 07:05:37 AM UTC 24 Sep 24 07:19:18 AM UTC 24 436370736989 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.2492808600 Sep 24 07:11:50 AM UTC 24 Sep 24 07:19:22 AM UTC 24 130664803245 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.876778383 Sep 24 07:12:41 AM UTC 24 Sep 24 07:19:25 AM UTC 24 328524845538 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.3452110788 Sep 24 07:19:23 AM UTC 24 Sep 24 07:19:36 AM UTC 24 5399241517 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.3933539755 Sep 24 07:04:52 AM UTC 24 Sep 24 07:19:39 AM UTC 24 548698565522 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.183989249 Sep 24 07:19:40 AM UTC 24 Sep 24 07:19:46 AM UTC 24 1585862518 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.2755167537 Sep 24 07:19:26 AM UTC 24 Sep 24 07:20:04 AM UTC 24 32811412658 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.2531601476 Sep 24 07:12:36 AM UTC 24 Sep 24 07:20:09 AM UTC 24 164983097376 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.2835415681 Sep 24 07:20:05 AM UTC 24 Sep 24 07:20:09 AM UTC 24 486838872 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.3096730353 Sep 24 07:20:10 AM UTC 24 Sep 24 07:20:14 AM UTC 24 6110507419 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.116633031 Sep 24 07:04:48 AM UTC 24 Sep 24 07:20:19 AM UTC 24 124994184759 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.368966164 Sep 24 07:13:31 AM UTC 24 Sep 24 07:20:23 AM UTC 24 490665048622 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2059532482 Sep 24 07:13:53 AM UTC 24 Sep 24 07:20:27 AM UTC 24 162148947958 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.3372975573 Sep 24 06:58:03 AM UTC 24 Sep 24 07:20:34 AM UTC 24 488539023071 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.2432525763 Sep 24 07:08:38 AM UTC 24 Sep 24 07:20:42 AM UTC 24 130010252785 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.3990458069 Sep 24 07:14:04 AM UTC 24 Sep 24 07:20:47 AM UTC 24 365298436324 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.597668690 Sep 24 07:17:54 AM UTC 24 Sep 24 07:20:53 AM UTC 24 41808363002 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.1735233137 Sep 24 07:15:59 AM UTC 24 Sep 24 07:20:56 AM UTC 24 325483111081 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.1197305381 Sep 24 07:18:43 AM UTC 24 Sep 24 07:20:56 AM UTC 24 159104880352 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.2508583084 Sep 24 07:20:54 AM UTC 24 Sep 24 07:20:57 AM UTC 24 4344820655 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2912182663 Sep 24 07:17:05 AM UTC 24 Sep 24 07:21:09 AM UTC 24 188412715378 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.2409376026 Sep 24 07:18:44 AM UTC 24 Sep 24 07:21:09 AM UTC 24 163494592673 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.1741925953 Sep 24 07:18:41 AM UTC 24 Sep 24 07:21:09 AM UTC 24 162387843677 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.3035393864 Sep 24 07:21:10 AM UTC 24 Sep 24 07:21:12 AM UTC 24 428683073 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3844526230 Sep 24 07:20:58 AM UTC 24 Sep 24 07:21:23 AM UTC 24 166089653024 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1956696791 Sep 24 07:08:16 AM UTC 24 Sep 24 07:21:29 AM UTC 24 606046333187 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.756636016 Sep 24 07:21:10 AM UTC 24 Sep 24 07:21:33 AM UTC 24 5674060957 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.394448879 Sep 24 06:58:05 AM UTC 24 Sep 24 07:21:41 AM UTC 24 598135435464 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3194048513 Sep 24 07:18:57 AM UTC 24 Sep 24 07:21:49 AM UTC 24 417906153123 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.3906944380 Sep 24 07:05:39 AM UTC 24 Sep 24 07:21:51 AM UTC 24 328806518378 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3179522301 Sep 24 07:09:50 AM UTC 24 Sep 24 07:21:53 AM UTC 24 548227635512 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.3852753161 Sep 24 07:19:18 AM UTC 24 Sep 24 07:21:59 AM UTC 24 169001200760 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.3232970148 Sep 24 06:58:43 AM UTC 24 Sep 24 07:22:02 AM UTC 24 492630599701 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.133161735 Sep 24 07:10:28 AM UTC 24 Sep 24 07:22:10 AM UTC 24 283286408661 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.305772619 Sep 24 07:03:38 AM UTC 24 Sep 24 07:22:22 AM UTC 24 504438234623 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.2476477634 Sep 24 07:22:00 AM UTC 24 Sep 24 07:22:23 AM UTC 24 4521429039 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.857360782 Sep 24 07:12:24 AM UTC 24 Sep 24 07:22:23 AM UTC 24 497116812420 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.191117623 Sep 24 07:22:24 AM UTC 24 Sep 24 07:22:27 AM UTC 24 315182315 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.2092378708 Sep 24 07:20:20 AM UTC 24 Sep 24 07:22:31 AM UTC 24 164780610591 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1038984486 Sep 24 07:22:23 AM UTC 24 Sep 24 07:22:34 AM UTC 24 6209211524 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3615820259 Sep 24 07:21:34 AM UTC 24 Sep 24 07:22:40 AM UTC 24 166486579214 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.3815289167 Sep 24 07:20:57 AM UTC 24 Sep 24 07:22:41 AM UTC 24 42515648148 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.458793816 Sep 24 06:58:10 AM UTC 24 Sep 24 07:22:41 AM UTC 24 561395086331 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.2867775103 Sep 24 07:15:25 AM UTC 24 Sep 24 07:22:45 AM UTC 24 75512936419 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.3174831399 Sep 24 07:22:28 AM UTC 24 Sep 24 07:22:53 AM UTC 24 6006047109 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.3446367029 Sep 24 07:20:10 AM UTC 24 Sep 24 07:23:02 AM UTC 24 166318665822 ps
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