Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19667

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3458

1

T17

5

T37

21

T28

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16925

1

T2

20

T3

20

T4

13

auto[1]

6200

1

T8

5

T14

21

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	55	1			T227	35		T199	5		T228	1
values[1]	723	1			T14	21		T20	1		T229	15
values[2]	979	1			T132	1		T130	16		T133	16
values[3]	669	1			T16	7		T17	5		T50	11
values[4]	2866	1			T15	1		T18	1		T19	11
values[5]	648	1			T37	21		T133	12		T155	47
values[6]	554	1			T128	1		T141	1		T134	1
values[7]	616	1			T13	5		T50	35		T129	11
values[8]	876	1			T81	1		T128	1		T230	3
values[9]	1162	1			T8	5		T28	7		T51	26
minimum	13977	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	932	1			T14	21		T20	1		T229	15
values[1]	1052	1			T16	7		T17	5		T132	1
values[2]	618	1			T38	12		T50	11		T140	16
values[3]	2820	1			T15	1		T18	1		T19	11
values[4]	710	1			T144	13		T134	1		T135	16
values[5]	488	1			T128	1		T141	1		T132	1
values[6]	733	1			T13	5		T50	35		T129	11
values[7]	688	1			T28	7		T81	1		T47	2
values[8]	962	1			T8	5		T128	1		T132	1
values[9]	114	1			T51	26		T94	4		T93	9
minimum	14008	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T14	10		T20	1		T133	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T229	8		T135	1		T231	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T16	5		T132	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T17	4		T130	16		T232	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T38	12		T141	1		T130	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T50	6		T140	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1549	1			T15	1		T18	1		T19	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T37	11		T133	1		T155	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T144	1		T134	1		T35	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T135	2		T155	12		T146	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T132	1		T86	9		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T128	1		T141	1		T136	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	4		T50	17		T129	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T129	1		T230	1		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T47	2		T148	6		T233	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T28	5		T81	1		T62	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T8	4		T152	4		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T128	1		T132	1		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T234	1		T235	8		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T51	16		T94	3		T93	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13879	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T236	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T14	11		T133	15		T237	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T229	7		T135	10		T238	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T16	2		T147	2		T96	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T17	1		T176	12		T237	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T152	12		T206	3		T154	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T50	5		T140	15		T147	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T19	10		T21	6		T142	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T37	10		T133	11		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T144	12		T35	12		T239	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T135	14		T155	12		T96	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T86	10		T240	27		T161	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T147	4		T241	2		T233	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	1		T50	18		T129	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T129	1		T230	2		T176	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T233	2		T93	2		T242	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T28	2		T62	1		T243	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T8	1		T152	4		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T206	10		T155	11		T244	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T234	11		T235	7		T213	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T51	10		T94	1		T93	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T6	1		T16	2		T46	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T227	20		T199	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T228	1		T245	1		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T14	10		T20	1		T237	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T229	8		T135	1		T231	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T132	1		T133	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T130	16		T232	14		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T16	5		T141	1		T152	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T17	4		T50	6		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T15	1		T18	1		T19	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T154	16		T86	4		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T35	14		T148	15		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T37	11		T133	1		T155	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T134	1		T146	14		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T128	1		T141	1		T135	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	4		T50	17		T129	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T129	1		T176	1		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T126	1		T148	6		T233	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T81	1		T128	1		T230	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T8	4		T47	2		T152	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T28	5		T51	16		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T227	15		T199	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T245	1		T246	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	11		T237	5		T164	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T229	7		T135	10		T238	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T133	15		T101	13		T237	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T147	6		T247	9		T248	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T16	2		T152	12		T147	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T17	1		T50	5		T140	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	943	1			T19	10		T21	6		T142	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T154	12		T86	3		T249	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T35	12		T239	2		T250	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T37	10		T133	11		T155	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T239	7		T251	12		T240	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T135	14		T147	4		T96	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	1		T50	18		T129	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T129	1		T176	12		T126	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T126	1		T233	2		T93	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T230	2		T62	1		T243	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T8	1		T152	4		T145	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T28	2		T51	10		T206	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T14	12		T20	1		T133	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T229	8		T135	11		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T16	7		T132	1		T147	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T17	4		T130	1		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T38	1		T141	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T50	6		T140	16		T147	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T15	1		T18	1		T19	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T37	11		T133	12		T155	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T144	13		T134	1		T35	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T135	16		T155	13		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T132	1		T86	11		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T128	1		T141	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T13	4		T50	19		T129	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T129	2		T230	3		T176	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T47	1		T148	1		T233	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T28	5		T81	1		T62	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T8	4		T152	5		T145	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T128	1		T132	1		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T234	12		T235	8		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T51	11		T94	3		T93	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13992	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T236	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	9		T237	11		T164	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T229	7		T231	13		T98	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T96	6		T101	4		T237	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T17	1		T130	15		T232	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T38	11		T130	10		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T50	5		T154	15		T252	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T142	10		T131	16		T253	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T37	10		T155	10		T126	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T35	13		T148	13		T247	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T155	11		T146	19		T96	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T86	8		T240	19		T187	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T136	8		T233	11		T238	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	1		T50	16		T129	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T126	12		T96	3		T254	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T47	1		T148	5		T233	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T28	2		T62	1		T136	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	1		T152	3		T243	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T155	14		T136	11		T244	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T235	7		T201	1		T193	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T51	15		T94	1		T93	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T236	15		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T227	16		T199	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T228	1		T245	2		T246	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T14	12		T20	1		T237	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T229	8		T135	11		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T132	1		T133	16		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T130	1		T232	1		T147	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T16	7		T141	1		T152	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T17	4		T50	6		T140	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T15	1		T18	1		T19	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T154	13		T86	4		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T35	13		T148	2		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T37	11		T133	12		T155	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T134	1		T146	1		T239	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T128	1		T141	1		T135	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	4		T50	19		T129	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T129	2		T176	13		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T126	2		T148	1		T233	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T81	1		T128	1		T230	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T8	4		T47	1		T152	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T28	5		T51	11		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T227	19		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	9		T237	11		T164	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T229	7		T231	13		T98	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T101	4		T237	5		T255	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T130	15		T232	13		T231	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T152	13		T154	17		T96	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T17	1		T50	5		T237	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T38	11		T142	10		T130	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T154	15		T86	3		T249	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T35	13		T148	13		T256	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T37	10		T155	21		T146	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T146	13		T240	11		T247	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T136	8		T96	8		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	1		T50	16		T129	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T136	18		T126	12		T96	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T148	5		T233	8		T93	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T62	1		T243	16		T254	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T8	1		T47	1		T152	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T28	2		T51	15		T155	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19685

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3440

1

T14

21

T20

1

T37

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16779

1

T2

20

T3

20

T4

13

auto[1]

6346

1

T15

1

T16

7

T18

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	35	1			T126	22		T29	1		T257	12
values[0]	93	1			T148	12		T208	10		T258	6
values[1]	688	1			T51	26		T231	14		T96	19
values[2]	2965	1			T15	1		T19	11		T20	1
values[3]	693	1			T8	5		T17	5		T133	12
values[4]	704	1			T50	35		T128	1		T129	9
values[5]	636	1			T141	1		T174	1		T135	1
values[6]	689	1			T132	1		T259	1		T35	26
values[7]	720	1			T14	21		T128	1		T141	1
values[8]	656	1			T18	1		T38	12		T132	1
values[9]	1269	1			T13	5		T16	7		T37	21
minimum	13977	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	988	1			T51	26		T132	1		T152	8
values[1]	2942	1			T15	1		T19	11		T20	1
values[2]	622	1			T8	5		T17	5		T128	1
values[3]	705	1			T50	35		T230	3		T135	1
values[4]	688	1			T141	1		T132	1		T174	1
values[5]	781	1			T14	21		T141	1		T134	1
values[6]	680	1			T18	1		T129	2		T132	1
values[7]	599	1			T38	12		T128	1		T206	4
values[8]	918	1			T13	5		T16	7		T37	21
values[9]	225	1			T81	1		T133	9		T147	3
minimum	13977	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T231	14		T148	12		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T51	16		T132	1		T152	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1600	1			T15	1		T19	1		T21	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T20	1		T47	2		T152	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	4		T17	4		T155	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T128	1		T129	5		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T50	17		T135	1		T154	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T230	1		T155	11		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T174	1		T259	1		T231	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T141	1		T132	1		T62	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T141	1		T134	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T14	10		T126	1		T233	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T18	1		T129	1		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T132	1		T136	9		T126	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T38	12		T35	7		T86	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T128	1		T206	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T13	4		T16	5		T28	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T37	11		T140	1		T130	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T81	1		T133	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T260	12		T200	1		T261	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T260	4		T262	10		T258	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T51	10		T152	4		T155	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T19	10		T21	6		T142	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T152	12		T263	10		T233	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	1		T17	1		T155	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T129	4		T133	11		T96	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T50	18		T154	15		T237	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T230	2		T155	12		T147	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T234	11		T249	6		T158	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T62	1		T243	10		T238	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T135	14		T96	6		T237	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	11		T126	1		T233	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T129	1		T176	12		T86	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T126	9		T35	12		T182	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T35	6		T86	3		T264	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T206	3		T145	12		T154	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T13	1		T16	2		T28	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T37	10		T140	15		T133	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T133	8		T147	2		T101	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T260	8		T261	13		T265	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1