Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19668

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3457

1

T8

5

T14

21

T17

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17203

1

T2

20

T3

20

T4

13

auto[1]

5922

1

T13

5

T14

21

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	431	1			T20	1		T134	2		T135	15
values[0]	15	1			T345	3		T346	1		T285	11
values[1]	629	1			T14	21		T16	7		T142	19
values[2]	758	1			T174	1		T230	3		T176	13
values[3]	609	1			T133	16		T62	3		T231	14
values[4]	635	1			T128	1		T145	13		T154	30
values[5]	587	1			T17	5		T128	1		T141	1
values[6]	653	1			T37	21		T38	12		T50	35
values[7]	941	1			T13	5		T28	7		T140	16
values[8]	3133	1			T8	5		T15	1		T18	1
values[9]	757	1			T50	11		T141	1		T129	2
minimum	13977	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	612	1			T14	21		T16	7		T132	1
values[1]	668	1			T133	16		T174	1		T230	3
values[2]	631	1			T62	3		T154	28		T231	14
values[3]	663	1			T17	5		T128	1		T130	16
values[4]	564	1			T128	1		T141	1		T47	2
values[5]	747	1			T37	21		T38	12		T28	7
values[6]	3203	1			T13	5		T15	1		T19	11
values[7]	792	1			T8	5		T18	1		T81	1
values[8]	820	1			T20	1		T50	11		T141	1
values[9]	218	1			T134	1		T280	21		T256	22
minimum	14207	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T16	5		T132	1		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	10		T147	1		T231	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T133	1		T230	1		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T174	1		T237	8		T302	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T154	16		T231	14		T237	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T62	2		T260	12		T276	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T130	16		T154	1		T237	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T17	4		T128	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T133	2		T153	11		T146	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T128	1		T141	1		T47	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T37	11		T140	1		T129	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T38	12		T28	5		T50	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1618	1			T13	4		T15	1		T19	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T51	16		T132	2		T130	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T81	1		T155	11		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	4		T18	1		T229	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T141	1		T206	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T20	1		T50	6		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T134	1		T280	1		T256	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T280	1		T270	6		T277	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13918	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T243	17		T262	1		T347	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	2		T147	4		T94	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T14	11		T147	2		T239	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T133	15		T230	2		T176	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T237	7		T302	5		T260	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T154	12		T237	5		T260	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T62	1		T260	8		T86	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T154	1		T237	10		T272	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T17	1		T145	12		T304	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T133	19		T101	13		T233	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T292	11		T303	9		T246	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T37	10		T140	15		T129	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T28	2		T50	18		T152	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T13	1		T19	10		T21	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T51	10		T206	3		T135	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T155	12		T147	6		T96	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T8	1		T229	7		T309	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T206	10		T135	14		T126	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T50	5		T129	1		T35	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T280	8		T256	12		T348	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T280	11		T270	1		T289	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	1		T16	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T243	10		T262	10		T272	16

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T134	2		T135	1		T126	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T20	1		T263	14		T249	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T345	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T346	1		T285	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T16	5		T142	11		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T14	10		T147	1		T243	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T230	1		T176	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T174	1		T231	14		T148	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T133	1		T231	14		T237	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T62	2		T260	12		T276	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T154	17		T237	6		T240	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T128	1		T145	1		T304	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T130	16		T133	2		T153	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T17	4		T128	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T37	11		T232	14		T146	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T38	12		T50	17		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	4		T140	1		T129	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T28	5		T132	1		T152	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1734	1			T15	1		T19	1		T21	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	4		T18	1		T51	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T141	1		T206	1		T155	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T50	6		T129	1		T136	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T135	14		T126	9		T243	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T263	10		T249	5		T280	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T345	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T285	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T16	2		T142	8		T147	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	11		T147	2		T243	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T230	2		T176	12		T94	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T237	7		T302	5		T260	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T133	15		T237	5		T260	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T62	1		T260	8		T86	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T154	13		T237	10		T240	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T145	12		T304	6		T294	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T133	19		T101	13		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T17	1		T303	9		T299	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T37	10		T154	15		T241	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T50	18		T155	12		T292	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	1		T140	15		T129	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T28	2		T152	4		T206	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T19	10		T21	6		T281	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	1		T51	10		T229	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T206	10		T155	12		T96	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T50	5		T129	1		T35	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T16	7		T132	1		T147	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	12		T147	3		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T133	16		T230	3		T176	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T174	1		T237	8		T302	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T154	13		T231	1		T237	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T62	2		T260	9		T276	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T130	1		T154	2		T237	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T17	4		T128	1		T145	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T133	21		T153	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T128	1		T141	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T37	11		T140	16		T129	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T38	1		T28	5		T50	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T13	4		T15	1		T19	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T51	11		T132	2		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T81	1		T155	13		T147	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	4		T18	1		T229	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T141	1		T206	11		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T20	1		T50	6		T129	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T134	1		T280	9		T256	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T280	12		T270	5		T277	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14034	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T243	11		T262	11		T347	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T94	1		T249	6		T247	27
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T14	9		T231	13		T148	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T146	19		T267	1		T233	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T237	7		T260	16		T238	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T154	15		T231	13		T237	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T62	1		T260	11		T276	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T130	15		T237	5		T240	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T17	1		T255	15		T304	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T153	10		T146	2		T101	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T47	1		T136	8		T148	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	10		T129	4		T232	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T38	11		T28	2		T50	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T13	1		T131	16		T152	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T51	15		T130	10		T155	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T155	10		T96	8		T276	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T8	1		T229	7		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T126	10		T96	3		T243	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T50	5		T35	13		T98	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T256	9		T348	12		T349	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T270	2		T277	11		T289	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T142	10		T244	12		T311	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T243	16		T343	1		T288	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T134	2		T135	15		T126	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T20	1		T263	11		T249	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T345	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T346	1		T285	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T16	7		T142	9		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	12		T147	3		T243	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T230	3		T176	13		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T174	1		T231	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T133	16		T231	1		T237	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T62	2		T260	9		T276	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T154	15		T237	11		T240	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T128	1		T145	13		T304	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T130	1		T133	21		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T17	4		T128	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T37	11		T232	1		T146	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T38	1		T50	19		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	4		T140	16		T129	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T28	5		T132	1		T152	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1405	1			T15	1		T19	11		T21	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	4		T18	1		T51	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T141	1		T206	11		T155	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T50	6		T129	2		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T126	10		T243	7		T256	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T263	13		T249	9		T158	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T142	10		T244	12		T249	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T14	9		T243	16		T93	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T146	19		T94	1		T267	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T231	13		T148	11		T237	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T231	13		T237	11		T260	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T62	1		T260	11		T276	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T154	15		T237	5		T240	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T304	9		T294	1		T295	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T130	15		T153	10		T101	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T17	1		T47	1		T136	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T37	10		T232	13		T146	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T38	11		T50	16		T155	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	1		T129	4		T152	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T28	2		T152	3		T155	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1401	1			T131	16		T253	12		T96	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	1		T51	15		T130	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T155	10		T96	3		T244	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T50	5		T136	11		T35	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9