Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19677

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3448

1

T17

5

T37

21

T28

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16922

1

T2

20

T3

20

T4

13

auto[1]

6203

1

T8

5

T14

21

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	214	1			T51	26		T134	1		T155	26
values[0]	41	1			T227	35		T228	1		T297	5
values[1]	743	1			T14	21		T20	1		T229	15
values[2]	971	1			T16	7		T132	1		T130	16
values[3]	673	1			T17	5		T50	11		T140	16
values[4]	2914	1			T15	1		T18	1		T19	11
values[5]	622	1			T133	12		T155	47		T146	20
values[6]	567	1			T128	1		T141	1		T134	1
values[7]	576	1			T13	5		T50	35		T129	11
values[8]	911	1			T81	1		T128	1		T230	3
values[9]	916	1			T8	5		T28	7		T132	1
minimum	13977	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	631	1			T14	21		T20	1		T133	16
values[1]	1033	1			T16	7		T17	5		T140	16
values[2]	622	1			T38	12		T50	11		T141	1
values[3]	2864	1			T15	1		T18	1		T19	11
values[4]	718	1			T144	13		T134	1		T135	16
values[5]	487	1			T128	1		T141	1		T132	1
values[6]	711	1			T13	5		T50	35		T129	11
values[7]	718	1			T28	7		T81	1		T128	1
values[8]	937	1			T8	5		T132	1		T152	8
values[9]	119	1			T51	26		T94	4		T262	11
minimum	14285	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T14	10		T20	1		T133	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T98	8		T321	1		T248	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T16	5		T132	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T17	4		T140	1		T130	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T38	12		T141	1		T130	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T50	6		T147	1		T154	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T15	1		T18	1		T19	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T37	11		T133	1		T155	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T144	1		T134	1		T35	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T135	2		T155	12		T146	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T132	1		T146	14		T86	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T128	1		T141	1		T136	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	4		T50	17		T129	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T129	1		T230	1		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T47	2		T148	6		T233	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T28	5		T81	1		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T8	4		T152	4		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T132	1		T174	1		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T262	1		T234	1		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T51	16		T94	3		T93	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13967	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T229	8		T135	1		T231	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	11		T133	15		T264	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T248	7		T160	11		T350	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T16	2		T147	2		T101	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T17	1		T140	15		T176	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T152	12		T206	3		T154	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T50	5		T147	6		T154	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	945	1			T19	10		T21	6		T142	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T37	10		T133	11		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T144	12		T35	12		T239	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T135	14		T155	12		T239	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T86	10		T240	27		T161	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T147	4		T96	10		T241	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	1		T50	18		T129	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T129	1		T230	2		T176	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T233	2		T93	2		T242	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T28	2		T62	1		T243	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	1		T152	4		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T206	10		T155	11		T244	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T262	10		T234	11		T258	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T51	10		T94	1		T93	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	1		T16	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T229	7		T135	10		T238	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T145	1		T262	1		T234	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T51	16		T134	1		T155	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T227	20		T297	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T228	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	10		T20	1		T237	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T229	8		T135	1		T231	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T16	5		T132	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T130	16		T232	14		T231	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T141	1		T152	14		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	4		T50	6		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1589	1			T15	1		T18	1		T19	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T37	11		T126	11		T154	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T35	14		T148	15		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T133	1		T155	23		T146	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T134	1		T146	14		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T128	1		T141	1		T135	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	4		T50	17		T129	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T129	1		T176	1		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T148	6		T233	9		T93	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T81	1		T128	1		T230	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T8	4		T47	2		T152	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T28	5		T132	1		T174	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T145	12		T262	10		T234	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T51	10		T155	11		T159	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T227	15		T297	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	11		T237	5		T164	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T229	7		T135	10		T238	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T16	2		T133	15		T101	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T247	9		T248	7		T160	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T152	12		T147	2		T154	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T17	1		T50	5		T140	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T19	10		T21	6		T142	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T37	10		T126	9		T154	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T35	12		T239	9		T256	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T133	11		T155	24		T239	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T251	12		T240	12		T247	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T135	14		T147	4		T96	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	1		T50	18		T129	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T129	1		T176	12		T126	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T233	2		T93	2		T238	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T230	2		T62	1		T243	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	1		T152	4		T243	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T28	2		T206	10		T94	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T14	12		T20	1		T133	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T98	1		T321	1		T248	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T16	7		T132	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T17	4		T140	16		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T38	1		T141	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T50	6		T147	7		T154	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T15	1		T18	1		T19	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T37	11		T133	12		T155	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T144	13		T134	1		T35	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T135	16		T155	13		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T132	1		T146	1		T86	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T128	1		T141	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	4		T50	19		T129	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T129	2		T230	3		T176	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T47	1		T148	1		T233	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T28	5		T81	1		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T8	4		T152	5		T145	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T132	1		T174	1		T206	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T262	11		T234	12		T258	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T51	11		T94	3		T93	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14069	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T229	8		T135	11		T231	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	9		T303	11		T311	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T98	7		T323	12		T283	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T101	4		T237	5		T255	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T17	1		T130	15		T232	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T38	11		T130	10		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T50	5		T154	15		T304	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T142	10		T131	16		T146	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T37	10		T155	10		T126	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T35	13		T148	13		T247	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T155	11		T146	19		T208	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T146	13		T86	8		T240	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T136	8		T96	8		T233	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	1		T50	16		T129	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T136	18		T126	12		T96	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T47	1		T148	5		T233	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T28	2		T62	1		T243	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	1		T152	3		T243	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T155	14		T136	11		T244	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T235	7		T193	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T51	15		T94	1		T93	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T237	11		T164	20		T266	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T229	7		T231	13		T238	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T145	13		T262	11		T234	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T51	11		T134	1		T155	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T227	16		T297	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T228	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T14	12		T20	1		T237	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T229	8		T135	11		T231	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T16	7		T132	1		T133	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T130	1		T232	1		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T141	1		T152	13		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T17	4		T50	6		T140	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T15	1		T18	1		T19	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T37	11		T126	10		T154	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T35	13		T148	2		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T133	12		T155	26		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T134	1		T146	1		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T128	1		T141	1		T135	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	4		T50	19		T129	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T129	2		T176	13		T205	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T148	1		T233	3		T93	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T81	1		T128	1		T230	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T8	4		T47	1		T152	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T28	5		T132	1		T174	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T235	7		T297	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T51	15		T155	14		T159	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T227	19		T297	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	9		T237	11		T164	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T229	7		T231	13		T98	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T101	4		T237	5		T255	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T130	15		T232	13		T231	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T152	13		T154	17		T96	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T17	1		T50	5		T237	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T38	11		T142	10		T130	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T37	10		T126	10		T154	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T35	13		T148	13		T256	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T155	21		T146	19		T208	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T146	13		T240	11		T247	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T136	8		T96	8		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	1		T50	16		T129	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T136	18		T126	12		T96	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T148	5		T233	8		T93	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T62	1		T243	16		T260	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	1		T47	1		T152	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T28	2		T136	11		T94	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9