Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19593

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3532

1

T8

5

T14

21

T17

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17223

1

T2

20

T3

20

T4

13

auto[1]

5902

1

T13

5

T14

21

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	41	1			T134	1		T243	20		T346	18
values[0]	25	1			T16	7		T132	1		T239	3
values[1]	615	1			T14	21		T142	19		T147	8
values[2]	718	1			T174	1		T230	3		T176	13
values[3]	594	1			T133	16		T62	3		T231	14
values[4]	709	1			T128	1		T145	13		T154	30
values[5]	625	1			T17	5		T50	35		T128	1
values[6]	648	1			T37	21		T38	12		T133	9
values[7]	939	1			T13	5		T28	7		T140	16
values[8]	3066	1			T8	5		T15	1		T18	1
values[9]	1168	1			T20	1		T50	11		T141	1
minimum	13977	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	776	1			T14	21		T16	7		T142	19
values[1]	687	1			T133	16		T174	1		T230	3
values[2]	747	1			T62	3		T154	30		T231	14
values[3]	499	1			T17	5		T128	1		T130	16
values[4]	607	1			T128	1		T141	1		T47	2
values[5]	786	1			T37	21		T38	12		T50	35
values[6]	3172	1			T13	5		T15	1		T18	1
values[7]	799	1			T8	5		T81	1		T229	15
values[8]	751	1			T20	1		T50	11		T141	1
values[9]	278	1			T35	26		T280	21		T256	22
minimum	14023	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T16	5		T142	11		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	10		T147	1		T148	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T133	1		T230	1		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T174	1		T231	14		T237	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T154	17		T231	14		T237	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T62	2		T302	1		T276	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T130	16		T153	11		T237	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T17	4		T128	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T133	2		T146	3		T101	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T128	1		T141	1		T47	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T37	11		T140	1		T129	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T38	12		T50	17		T152	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1622	1			T13	4		T15	1		T19	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T18	1		T28	5		T51	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T81	1		T155	11		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	4		T229	8		T136	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T141	1		T206	1		T134	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T20	1		T50	6		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T280	2		T256	10		T351	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T35	14		T160	1		T277	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13900	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T262	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T16	2		T142	8		T94	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	11		T147	2		T243	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T133	15		T230	2		T176	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T237	7		T260	18		T238	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T154	13		T237	5		T260	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T62	1		T302	5		T86	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T237	10		T272	8		T352	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T17	1		T145	12		T304	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T133	19		T101	13		T233	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T292	11		T303	9		T299	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T37	10		T140	15		T129	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T50	18		T152	4		T176	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T13	1		T19	10		T21	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T28	2		T51	10		T206	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T155	12		T147	6		T96	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	1		T229	7		T309	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T206	10		T135	14		T126	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T50	5		T129	1		T263	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T280	19		T256	12		T351	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T35	12		T160	2		T289	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T6	1		T16	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T262	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T134	1		T243	8		T291	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T346	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T16	5		T132	1		T239	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T353	1		T275	3		T346	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T142	11		T147	1		T244	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	10		T147	1		T243	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T230	1		T176	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T174	1		T231	14		T148	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T133	1		T231	14		T237	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T62	2		T260	29		T276	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T154	17		T237	6		T240	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T128	1		T145	1		T304	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T130	16		T133	1		T153	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T17	4		T50	17		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T37	11		T133	1		T232	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T38	12		T206	1		T155	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	4		T140	1		T129	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T28	5		T132	1		T152	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1706	1			T15	1		T19	1		T21	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	4		T18	1		T51	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T141	1		T206	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T20	1		T50	6		T129	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T243	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T346	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T16	2		T239	2		T345	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T353	2		T275	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T142	8		T147	4		T244	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	11		T147	2		T243	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T230	2		T176	12		T94	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T237	7		T302	5		T258	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T133	15		T237	5		T260	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T62	1		T260	18		T86	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T154	13		T237	10		T240	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T145	12		T304	6		T294	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T133	11		T101	13		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T17	1		T50	18		T303	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T37	10		T133	8		T154	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T206	3		T155	12		T241	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	1		T140	15		T129	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T28	2		T152	4		T176	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T19	10		T21	6		T281	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T8	1		T51	10		T229	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T206	10		T135	14		T155	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T50	5		T129	1		T35	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T16	7		T142	9		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T14	12		T147	3		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T133	16		T230	3		T176	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T174	1		T231	1		T237	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T154	15		T231	1		T237	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T62	2		T302	6		T276	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T130	1		T153	1		T237	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T17	4		T128	1		T145	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T133	21		T146	1		T101	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T128	1		T141	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	11		T140	16		T129	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T38	1		T50	19		T152	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T13	4		T15	1		T19	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T18	1		T28	5		T51	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T81	1		T155	13		T147	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	4		T229	8		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T141	1		T206	11		T134	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T20	1		T50	6		T129	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T280	21		T256	13		T351	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T35	13		T160	3		T277	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13992	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T262	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T142	10		T94	1		T244	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	9		T148	11		T243	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T146	19		T267	1		T233	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T231	13		T237	7		T260	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T154	15		T231	13		T237	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T62	1		T276	5		T86	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T130	15		T153	10		T237	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T17	1		T255	15		T304	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T146	2		T101	4		T233	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T47	1		T136	8		T148	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T37	10		T129	4		T232	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T38	11		T50	16		T152	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T13	1		T131	16		T152	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T28	2		T51	15		T130	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T155	10		T96	8		T276	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T8	1		T229	7		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T126	10		T96	3		T243	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T50	5		T98	7		T263	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T256	9		T351	10		T319	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T35	13		T277	11		T289	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T247	20		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T134	1		T243	13		T291	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T346	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T16	7		T132	1		T239	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T353	3		T275	4		T346	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T142	9		T147	5		T244	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	12		T147	3		T243	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T230	3		T176	13		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T174	1		T231	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T133	16		T231	1		T237	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T62	2		T260	20		T276	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T154	15		T237	11		T240	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T128	1		T145	13		T304	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T130	1		T133	12		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T17	4		T50	19		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T37	11		T133	9		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T38	1		T206	4		T155	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	4		T140	16		T129	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T28	5		T132	1		T152	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T15	1		T19	11		T21	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	4		T18	1		T51	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T141	1		T206	11		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T20	1		T50	6		T129	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T243	7		T291	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T346	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T275	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T142	10		T244	12		T249	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T14	9		T243	16		T93	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T146	19		T94	1		T267	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T231	13		T148	11		T237	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T231	13		T237	11		T260	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T62	1		T260	27		T276	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T154	15		T237	5		T240	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T304	9		T294	1		T295	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T130	15		T153	10		T101	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T17	1		T50	16		T47	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T37	10		T232	13		T146	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T38	11		T155	11		T292	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T13	1		T129	4		T152	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T28	2		T152	3		T155	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T131	16		T253	12		T96	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	1		T51	15		T130	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T155	10		T126	10		T244	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T50	5		T136	11		T35	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9