Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19761

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3364

1

T14

21

T18

1

T37

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16805

1

T2

20

T3

20

T4

13

auto[1]

6320

1

T13

5

T14

21

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	38	1			T263	24		T310	1		T354	1
values[0]	48	1			T94	4		T302	6		T240	24
values[1]	604	1			T14	21		T38	12		T141	1
values[2]	527	1			T128	1		T141	1		T132	1
values[3]	603	1			T17	5		T129	9		T229	15
values[4]	595	1			T16	7		T142	19		T130	11
values[5]	3013	1			T15	1		T19	11		T21	7
values[6]	937	1			T8	5		T13	5		T152	8
values[7]	711	1			T18	1		T37	21		T81	1
values[8]	686	1			T20	1		T28	7		T50	11
values[9]	1386	1			T50	35		T133	37		T232	14
minimum	13977	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	686	1			T14	21		T38	12		T141	1
values[1]	586	1			T128	1		T141	1		T51	26
values[2]	632	1			T17	5		T129	9		T135	11
values[3]	2942	1			T15	1		T16	7		T19	11
values[4]	767	1			T176	13		T134	1		T146	23
values[5]	875	1			T8	5		T13	5		T18	1
values[6]	540	1			T37	21		T81	1		T128	1
values[7]	803	1			T20	1		T28	7		T50	11
values[8]	1109	1			T50	35		T133	28		T232	14
values[9]	170	1			T135	15		T62	3		T231	14
minimum	14015	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T141	1		T132	2		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	10		T38	12		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T128	1		T259	1		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T141	1		T51	16		T47	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T17	4		T136	12		T233	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T129	5		T135	1		T155	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1682	1			T15	1		T16	5		T19	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T144	1		T162	1		T86	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T176	1		T134	1		T146	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T146	3		T137	4		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T8	4		T13	4		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T18	1		T152	4		T205	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T129	1		T206	1		T148	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T37	11		T81	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T20	1		T28	5		T50	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T140	1		T152	14		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T50	17		T133	1		T232	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T133	1		T155	11		T96	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T135	1		T231	14		T148	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T62	2		T280	1		T158	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T91	1		T336	18		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T154	12		T302	5		T260	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	11		T206	10		T94	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T126	1		T147	4		T243	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T51	10		T229	7		T147	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T17	1		T233	11		T239	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T129	4		T135	10		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T16	2		T19	10		T21	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T144	12		T86	10		T249	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T176	12		T251	12		T280	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T154	1		T35	6		T101	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	1		T13	1		T230	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T152	4		T126	9		T96	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T129	1		T206	3		T260	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T37	10		T96	3		T237	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T28	2		T50	5		T126	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T140	15		T152	12		T133	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T50	18		T133	15		T176	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T133	11		T155	12		T96	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T135	14		T263	10		T89	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T62	1		T280	8		T158	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T91	11		T336	8		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T263	14		T354	1		T355	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T310	1		T300	8		T356	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T302	1		T240	12		T157	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T94	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T141	1		T132	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	10		T38	12		T51	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T128	1		T132	1		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T141	1		T47	2		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T17	4		T153	11		T136	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T129	5		T229	8		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T16	5		T142	11		T130	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T135	1		T243	8		T244	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1714	1			T15	1		T19	1		T21	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T144	1		T146	3		T137	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T8	4		T13	4		T230	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T152	4		T205	1		T146	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T129	1		T132	1		T206	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T18	1		T37	11		T81	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T20	1		T28	5		T50	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T140	1		T292	12		T238	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	378	1			T50	17		T133	1		T232	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T133	2		T155	11		T62	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T263	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T300	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T302	5		T240	12		T178	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T94	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T154	12		T260	8		T323	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	11		T51	10		T206	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T126	1		T147	4		T243	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T147	6		T237	7		T249	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T17	1		T233	11		T239	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T129	4		T229	7		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T16	2		T142	8		T237	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T135	10		T243	12		T244	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T19	10		T21	6		T281	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T144	12		T154	1		T35	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T8	1		T13	1		T230	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T152	4		T126	9		T237	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T129	1		T206	3		T147	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T37	10		T152	12		T96	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T28	2		T50	5		T154	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T140	15		T292	11		T238	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T50	18		T133	15		T176	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T133	19		T155	12		T62	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T141	1		T132	2		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T14	12		T38	1		T206	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T128	1		T259	1		T126	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T141	1		T51	11		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T17	4		T136	1		T233	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T129	5		T135	11		T155	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T15	1		T16	7		T19	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T144	13		T162	1		T86	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T176	13		T134	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T146	1		T137	4		T154	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T8	4		T13	4		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T18	1		T152	5		T205	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T129	2		T206	4		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T37	11		T81	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T20	1		T28	5		T50	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T140	16		T152	13		T133	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T50	19		T133	16		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T133	12		T155	13		T96	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T135	15		T231	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T62	2		T280	9		T158	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T91	12		T336	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T154	15		T260	11		T240	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	9		T38	11		T94	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T231	13		T243	16		T254	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T51	15		T47	1		T229	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T17	1		T136	11		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T129	4		T155	11		T243	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T142	10		T130	10		T131	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T86	8		T249	6		T303	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T146	19		T136	18		T163	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T146	2		T35	6		T101	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	1		T13	1		T260	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T152	3		T146	13		T126	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T148	5		T260	5		T304	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T37	10		T130	15		T96	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T28	2		T50	5		T136	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T152	13		T292	11		T238	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T50	16		T232	13		T155	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T155	10		T96	6		T148	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T231	13		T148	2		T263	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T62	1		T158	10		T329	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T336	17		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T263	11		T354	1		T355	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T310	1		T300	3		T356	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T302	6		T240	13		T157	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T94	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T141	1		T132	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	12		T38	1		T51	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T128	1		T132	1		T126	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T141	1		T47	1		T147	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T17	4		T153	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T129	5		T229	8		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T16	7		T142	9		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T135	11		T243	13		T244	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T15	1		T19	11		T21	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T144	13		T146	1		T137	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T8	4		T13	4		T230	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T152	5		T205	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T129	2		T132	1		T206	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T18	1		T37	11		T81	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T20	1		T28	5		T50	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T140	16		T292	12		T238	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	356	1			T50	19		T133	16		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	410	1			T133	21		T155	13		T62	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T263	13		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T300	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T240	11		T178	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T94	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T154	15		T260	11		T329	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	9		T38	11		T51	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T231	13		T243	16		T182	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T47	1		T237	7		T255	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T17	1		T153	10		T136	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T129	4		T229	7		T155	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T142	10		T130	10		T146	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T243	7		T244	4		T86	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T131	16		T136	18		T253	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T146	2		T35	6		T101	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T8	1		T13	1		T260	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T152	3		T146	13		T126	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T148	5		T260	5		T304	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T37	10		T130	15		T152	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T28	2		T50	5		T154	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T292	11		T238	14		T333	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T50	16		T232	13		T155	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T155	10		T62	1		T96	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9