Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19668

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3457

1

T8

5

T16

7

T17

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16952

1

T2

20

T3

20

T4

13

auto[1]

6173

1

T8

5

T13

5

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	380	1			T135	11		T94	4		T96	19
values[0]	60	1			T182	16		T357	13		T326	12
values[1]	761	1			T37	21		T28	7		T229	15
values[2]	694	1			T17	5		T128	1		T176	13
values[3]	730	1			T14	21		T129	11		T230	3
values[4]	520	1			T8	5		T13	5		T50	11
values[5]	626	1			T18	1		T20	1		T141	1
values[6]	808	1			T50	35		T133	16		T176	13
values[7]	608	1			T81	1		T128	1		T141	1
values[8]	636	1			T16	7		T38	12		T140	16
values[9]	3325	1			T15	1		T19	11		T21	7
minimum	13977	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	812	1			T37	21		T128	1		T229	15
values[1]	684	1			T14	21		T17	5		T28	7
values[2]	647	1			T129	11		T155	26		T147	7
values[3]	531	1			T8	5		T13	5		T18	1
values[4]	734	1			T20	1		T141	1		T232	14
values[5]	679	1			T50	35		T81	1		T47	2
values[6]	2972	1			T15	1		T19	11		T21	7
values[7]	571	1			T16	7		T140	16		T142	19
values[8]	1143	1			T132	1		T144	13		T152	26
values[9]	144	1			T130	11		T147	5		T255	16
minimum	14208	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T37	11		T128	1		T146	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T229	8		T134	1		T136	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T14	10		T28	5		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T17	4		T230	1		T153	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T129	5		T155	15		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T129	1		T35	7		T276	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T13	4		T50	6		T152	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T8	4		T18	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T141	1		T232	14		T155	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T20	1		T145	1		T146	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T133	1		T176	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T50	17		T81	1		T47	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1712	1			T15	1		T19	1		T21	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T128	1		T135	1		T126	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T140	1		T142	11		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T16	5		T132	1		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T133	1		T259	1		T279	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T132	1		T144	1		T152	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T130	11		T255	16		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T147	1		T208	11		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13945	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T137	4		T162	1		T86	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T37	10		T154	15		T86	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T229	7		T241	2		T247	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	11		T28	2		T176	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T17	1		T230	2		T155	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T129	4		T155	11		T147	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T129	1		T35	6		T89	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T13	1		T50	5		T152	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	1		T206	10		T267	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T155	12		T260	8		T244	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T145	12		T243	22		T233	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T133	15		T176	12		T96	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T50	18		T35	12		T239	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T19	10		T21	6		T51	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T135	14		T126	9		T233	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T140	15		T142	8		T133	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T16	2		T237	7		T234	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T133	11		T96	10		T302	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T144	12		T152	12		T135	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T282	13		T288	5		T358	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T147	4		T271	2		T322	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T16	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T86	3		T264	1		T182	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T96	9		T199	1		T282	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T135	1		T94	3		T292	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T357	3		T326	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T182	5		T324	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T37	11		T28	5		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T229	8		T134	1		T136	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T128	1		T176	1		T154	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T17	4		T147	1		T148	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	10		T129	5		T155	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T129	1		T230	1		T153	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	4		T50	6		T152	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	4		T132	1		T276	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T141	1		T232	14		T347	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T18	1		T20	1		T130	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T133	1		T176	1		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T50	17		T231	14		T35	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T141	1		T51	16		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T81	1		T128	1		T47	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T38	12		T140	1		T142	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T16	5		T152	14		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1720	1			T15	1		T19	1		T21	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T132	2		T144	1		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T96	10		T199	12		T282	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T135	10		T94	1		T292	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T357	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T182	11		T324	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T37	10		T28	2		T233	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T229	7		T241	2		T86	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T176	12		T154	15		T237	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T17	1		T147	2		T242	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	11		T129	4		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T129	1		T230	2		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T13	1		T50	5		T152	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	1		T239	2		T305	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T238	7		T323	10		T284	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T206	10		T145	12		T243	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T133	15		T176	12		T155	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T50	18		T35	12		T243	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T51	10		T96	6		T262	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T135	14		T126	9		T233	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T140	15		T142	8		T133	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T16	2		T152	12		T237	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T19	10		T21	6		T281	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T144	12		T147	4		T260	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T37	11		T128	1		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T229	8		T134	1		T136	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	12		T28	5		T176	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T17	4		T230	3		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T129	5		T155	12		T147	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T129	2		T35	7		T276	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T13	4		T50	6		T152	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	4		T18	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T141	1		T232	1		T155	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T20	1		T145	13		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T133	16		T176	13		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T50	19		T81	1		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T15	1		T19	11		T21	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T128	1		T135	15		T126	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T140	16		T142	9		T133	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T16	7		T132	1		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T133	12		T259	1		T279	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T132	1		T144	13		T152	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T130	1		T255	1		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T147	5		T208	1		T271	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14024	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T137	4		T162	1		T86	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T37	10		T146	19		T154	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T229	7		T136	26		T247	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	9		T28	2		T237	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T17	1		T153	10		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T129	4		T155	14		T260	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T35	6		T276	6		T89	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T13	1		T50	5		T152	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	1		T130	15		T267	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T232	13		T155	10		T260	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T146	13		T231	13		T243	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T96	3		T249	6		T238	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T50	16		T47	1		T35	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T38	11		T51	15		T131	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T126	10		T98	7		T233	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T142	10		T62	1		T101	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T237	7		T295	14		T311	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T96	8		T148	2		T164	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T152	13		T94	1		T260	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T130	10		T255	15		T296	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T208	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T233	11		T277	11		T357	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T86	3		T182	4		T275	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T96	11		T199	13		T282	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T135	11		T94	3		T292	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T357	11		T326	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T182	12		T324	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T37	11		T28	5		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T229	8		T134	1		T136	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T128	1		T176	13		T154	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	4		T147	3		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	12		T129	5		T155	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T129	2		T230	3		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T13	4		T50	6		T152	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T8	4		T132	1		T276	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T141	1		T232	1		T347	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T18	1		T20	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T133	16		T176	13		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T50	19		T231	1		T35	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T141	1		T51	11		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T81	1		T128	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T38	1		T140	16		T142	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T16	7		T152	13		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T15	1		T19	11		T21	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T132	2		T144	13		T147	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T96	8		T316	11		T333	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T94	1		T292	11		T158	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T357	2		T326	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T182	4		T324	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T37	10		T28	2		T146	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T229	7		T136	26		T86	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T154	17		T237	5		T263	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	1		T148	11		T276	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	9		T129	4		T155	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T153	10		T155	11		T154	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T13	1		T50	5		T152	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T8	1		T276	5		T208	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T232	13		T238	5		T323	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T130	15		T146	13		T243	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T155	10		T96	3		T260	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T50	16		T231	13		T35	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T51	15		T146	2		T136	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T47	1		T126	10		T98	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T38	11		T142	10		T62	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T152	13		T237	7		T295	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T130	10		T131	16		T253	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T260	5		T208	10		T294	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9