Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19634

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3491

1

T14

21

T20

1

T37

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16814

1

T2

20

T3

20

T4

13

auto[1]

6311

1

T15

1

T16

7

T18

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	285	1			T16	7		T28	7		T81	1
values[0]	83	1			T148	12		T208	10		T247	17
values[1]	668	1			T51	26		T231	14		T96	19
values[2]	3011	1			T15	1		T19	11		T20	1
values[3]	694	1			T8	5		T17	5		T129	9
values[4]	665	1			T50	35		T128	1		T230	3
values[5]	665	1			T141	1		T174	1		T62	3
values[6]	761	1			T14	21		T132	1		T259	1
values[7]	681	1			T141	1		T129	2		T134	1
values[8]	632	1			T18	1		T128	1		T132	1
values[9]	1003	1			T13	5		T37	21		T38	12
minimum	13977	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	759	1			T51	26		T132	1		T130	11
values[1]	2947	1			T15	1		T19	11		T20	1
values[2]	621	1			T8	5		T17	5		T129	9
values[3]	653	1			T50	35		T128	1		T230	3
values[4]	770	1			T141	1		T174	1		T62	3
values[5]	783	1			T14	21		T141	1		T132	1
values[6]	646	1			T129	2		T132	1		T176	13
values[7]	504	1			T18	1		T38	12		T128	1
values[8]	1059	1			T13	5		T16	7		T37	21
values[9]	164	1			T28	7		T133	9		T163	16
minimum	14219	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T130	11		T148	12		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T51	16		T132	1		T152	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1600	1			T15	1		T19	1		T21	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T20	1		T47	2		T152	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	4		T17	4		T155	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T129	5		T133	1		T155	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T50	17		T135	1		T237	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T128	1		T230	1		T237	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T174	1		T259	1		T154	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T141	1		T62	2		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T141	1		T134	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T14	10		T132	1		T35	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T129	1		T176	1		T146	34
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T132	1		T136	9		T126	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T18	1		T38	12		T35	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T128	1		T206	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T13	4		T16	5		T50	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T37	11		T140	1		T130	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T28	5		T133	1		T93	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T163	16		T236	14		T359	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13933	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T233	12		T247	8		T266	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T262	10		T258	5		T242	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T51	10		T152	4		T155	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T19	10		T21	6		T142	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T152	12		T263	10		T233	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T8	1		T17	1		T155	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T129	4		T133	11		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T50	18		T237	10		T267	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T230	2		T237	5		T260	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T154	15		T249	6		T272	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T62	1		T126	1		T147	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T135	14		T96	6		T237	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	11		T35	12		T233	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T129	1		T176	12		T86	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T126	9		T235	7		T182	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T35	6		T86	3		T264	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T206	3		T145	12		T154	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T13	1		T16	2		T50	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T37	10		T140	15		T133	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T28	2		T133	8		T93	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T265	4		T203	18		T360	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T6	1		T16	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T233	11		T247	9		T266	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T16	5		T28	5		T81	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T29	1		T165	1		T312	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T148	12		T208	10		T268	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T247	8		T246	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T231	14		T162	1		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T51	16		T96	9		T233	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1592	1			T15	1		T19	1		T21	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T20	1		T132	1		T47	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	4		T17	4		T232	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T129	5		T133	1		T155	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T50	17		T135	1		T237	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T128	1		T230	1		T237	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T174	1		T154	18		T231	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T141	1		T62	2		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T259	1		T96	7		T237	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	10		T132	1		T35	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T141	1		T129	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T136	9		T255	16		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T18	1		T176	1		T146	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T128	1		T132	1		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T13	4		T38	12		T50	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T37	11		T140	1		T130	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T16	2		T28	2		T126	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T312	1		T360	9		T361	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T268	7		T269	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T247	9		T246	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T258	5		T242	4		T270	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T51	10		T96	10		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T19	10		T21	6		T142	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T152	16		T155	11		T263	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	1		T17	1		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T129	4		T133	11		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T50	18		T237	10		T267	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T230	2		T237	5		T260	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T154	15		T249	6		T272	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T62	1		T126	1		T147	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T96	6		T237	7		T227	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	11		T35	12		T233	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T129	1		T135	14		T234	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T247	13		T242	12		T235	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T176	12		T35	6		T86	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T206	3		T145	12		T126	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T13	1		T50	5		T144	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T37	10		T140	15		T133	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T130	1		T148	1		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T51	11		T132	1		T152	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T15	1		T19	11		T21	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T20	1		T47	1		T152	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T8	4		T17	4		T155	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T129	5		T133	12		T155	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T50	19		T135	1		T237	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T128	1		T230	3		T237	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T174	1		T259	1		T154	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T141	1		T62	2		T126	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T141	1		T134	1		T135	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T14	12		T132	1		T35	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T129	2		T176	13		T146	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T132	1		T136	1		T126	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T18	1		T38	1		T35	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T128	1		T206	4		T145	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	394	1			T13	4		T16	7		T50	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T37	11		T140	16		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T28	5		T133	9		T93	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T163	1		T236	1		T359	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14018	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T233	12		T247	10		T266	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T130	10		T148	11		T208	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T51	15		T152	3		T155	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T142	10		T131	16		T232	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T47	1		T152	13		T263	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T8	1		T17	1		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T129	4		T155	10		T154	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T50	16		T237	5		T267	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T237	11		T260	16		T276	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T154	17		T231	13		T148	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T62	1		T98	7		T243	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T96	6		T237	7		T227	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	9		T35	13		T93	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T146	32		T86	8		T249	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T136	8		T126	10		T255	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T38	11		T35	6		T86	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T146	2		T136	11		T94	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T13	1		T50	5		T229	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T37	10		T130	15		T260	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T28	2		T93	4		T158	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T163	15		T236	13		T265	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T231	13		T273	1		T296	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T233	11		T247	7		T266	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T16	7		T28	5		T81	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T29	1		T165	1		T312	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T148	1		T208	1		T268	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T247	10		T246	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T231	1		T162	1		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T51	11		T96	11		T233	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T15	1		T19	11		T21	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T20	1		T132	1		T47	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	4		T17	4		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T129	5		T133	12		T155	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T50	19		T135	1		T237	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T128	1		T230	3		T237	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T174	1		T154	16		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T141	1		T62	2		T126	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T259	1		T96	7		T237	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	12		T132	1		T35	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T141	1		T129	2		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T136	1		T255	1		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T18	1		T176	13		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T128	1		T132	1		T206	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T13	4		T38	1		T50	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T37	11		T140	16		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T28	2		T126	12		T243	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T236	13		T319	9		T360	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T148	11		T208	9		T268	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T247	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T231	13		T273	1		T270	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T51	15		T96	8		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T142	10		T130	10		T131	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T47	1		T152	16		T155	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T8	1		T17	1		T232	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T129	4		T155	10		T154	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T50	16		T237	5		T267	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T237	11		T260	16		T276	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T154	17		T231	13		T148	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T62	1		T243	16		T238	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T96	6		T237	7		T273	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	9		T35	13		T98	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T146	13		T249	9		T238	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T136	8		T255	15		T247	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T146	19		T35	6		T86	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T146	2		T136	11		T126	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T13	1		T38	11		T50	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T37	10		T130	15		T163	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9