Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17371

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

5754

1

T13

5

T14

21

T15

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17131

1

T2

20

T3

20

T4

13

auto[1]

5994

1

T8

5

T13

5

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	276	1			T141	1		T134	1		T62	3
values[0]	44	1			T13	5		T146	3		T288	6
values[1]	742	1			T145	13		T147	7		T243	27
values[2]	619	1			T129	9		T174	1		T176	13
values[3]	829	1			T50	11		T229	15		T133	9
values[4]	488	1			T8	5		T20	1		T37	21
values[5]	654	1			T51	26		T129	2		T130	27
values[6]	697	1			T28	7		T81	1		T132	1
values[7]	759	1			T38	12		T128	1		T142	19
values[8]	532	1			T16	7		T206	11		T134	1
values[9]	3508	1			T14	21		T15	1		T17	5
minimum	13977	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	841	1			T176	13		T145	13		T147	7
values[1]	2939	1			T15	1		T19	11		T21	7
values[2]	689	1			T37	21		T229	15		T133	9
values[3]	531	1			T8	5		T20	1		T141	1
values[4]	692	1			T51	26		T129	2		T130	27
values[5]	726	1			T28	7		T81	1		T132	1
values[6]	652	1			T38	12		T128	1		T142	19
values[7]	607	1			T16	7		T50	35		T206	11
values[8]	1121	1			T14	21		T17	5		T18	1
values[9]	179	1			T134	1		T126	22		T162	1
minimum	14148	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T147	1		T96	7		T234	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T176	1		T145	1		T263	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T50	6		T129	5		T174	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1648	1			T15	1		T19	1		T21	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T94	3		T278	1		T237	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T37	11		T229	8		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T8	4		T141	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T20	1		T126	11		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T130	27		T152	14		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T51	16		T129	1		T152	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T28	5		T133	1		T155	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T81	1		T132	1		T146	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T142	11		T133	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T38	12		T128	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	5		T50	17		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T206	1		T146	20		T35	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T17	4		T128	1		T47	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T14	10		T18	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T134	1		T89	4		T208	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T126	13		T162	1		T274	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13897	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T13	4		T243	17		T241	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T147	6		T96	6		T242	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T176	12		T145	12		T263	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T50	5		T129	4		T155	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	914	1			T19	10		T21	6		T281	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T94	1		T237	7		T238	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T37	10		T229	7		T133	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	1		T230	2		T241	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T126	9		T147	2		T244	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T152	12		T96	3		T309	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T51	10		T129	1		T152	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T28	2		T133	11		T155	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T101	13		T239	2		T164	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T142	8		T133	15		T135	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T135	10		T282	19		T283	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T16	2		T50	18		T154	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T206	10		T35	12		T267	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T17	1		T176	12		T147	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T14	11		T140	15		T144	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T89	3		T199	7		T285	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T126	9		T274	16		T289	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	1		T16	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T13	1		T243	10		T240	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T134	1		T154	18		T89	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T141	1		T62	2		T279	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T146	3		T288	1		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T13	4		T362	16		T363	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T147	1		T234	1		T242	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T145	1		T243	17		T263	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T129	5		T174	1		T96	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T176	1		T155	15		T237	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T50	6		T155	11		T148	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T229	8		T133	1		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T8	4		T141	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T20	1		T37	11		T126	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T130	27		T152	14		T98	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T51	16		T129	1		T152	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T28	5		T133	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T81	1		T132	1		T101	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T142	11		T133	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T38	12		T128	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T16	5		T134	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T206	1		T35	14		T267	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T17	4		T50	17		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1754	1			T14	10		T15	1		T18	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T154	15		T89	3		T269	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T62	1		T158	10		T312	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T288	5		T290	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T13	1		T363	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T147	6		T242	12		T280	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T145	12		T243	10		T263	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T129	4		T96	6		T244	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T176	12		T155	11		T237	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T50	5		T155	12		T237	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T229	7		T133	8		T206	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T8	1		T230	2		T94	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T37	10		T126	9		T147	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T152	12		T86	10		T264	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T51	10		T129	1		T152	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T28	2		T133	11		T96	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T101	13		T237	10		T239	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T142	8		T133	15		T155	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T135	10		T282	19		T350	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T16	2		T135	14		T239	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T206	10		T35	12		T267	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T17	1		T50	18		T176	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1121	1			T14	11		T19	10		T21	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T147	7		T96	7		T234	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T176	13		T145	13		T263	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T50	6		T129	5		T174	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1243	1			T15	1		T19	11		T21	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T94	3		T278	1		T237	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T37	11		T229	8		T133	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	4		T141	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T20	1		T126	10		T147	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T130	2		T152	13		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T51	11		T129	2		T152	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T28	5		T133	12		T155	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T81	1		T132	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T142	9		T133	16		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T38	1		T128	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T16	7		T50	19		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T206	11		T146	1		T35	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T17	4		T128	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T14	12		T18	1		T140	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T134	1		T89	4		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T126	10		T162	1		T274	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14003	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T13	4		T243	11		T241	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T96	6		T208	9		T182	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T263	13		T260	16		T292	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T50	5		T129	4		T155	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1319	1			T131	16		T155	14		T136	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T94	1		T237	7		T238	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T37	10		T229	7		T243	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T8	1		T98	7		T238	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T126	10		T244	12		T294	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T130	25		T152	13		T96	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T51	15		T152	3		T237	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T28	2		T155	11		T231	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T146	13		T101	4		T148	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T142	10		T93	2		T247	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T38	11		T232	13		T231	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T50	16		T154	15		T96	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T146	19		T35	13		T267	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T17	1		T47	1		T153	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T14	9		T62	1		T136	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T89	3		T208	10		T199	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T126	12		T274	14		T289	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T146	2		T364	3		T365	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T13	1		T243	16		T240	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T134	1		T154	16		T89	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T141	1		T62	2		T279	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T146	1		T288	6		T290	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T13	4		T362	1		T363	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T147	7		T234	1		T242	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T145	13		T243	11		T263	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T129	5		T174	1		T96	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T176	13		T155	12		T237	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T50	6		T155	13		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T229	8		T133	9		T206	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T8	4		T141	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T20	1		T37	11		T126	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T130	2		T152	13		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T51	11		T129	2		T152	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T28	5		T133	12		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T81	1		T132	1		T101	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T142	9		T133	16		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T38	1		T128	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T16	7		T134	1		T135	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T206	11		T35	13		T267	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T17	4		T50	19		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1469	1			T14	12		T15	1		T18	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T154	17		T89	3		T187	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T62	1		T158	10		T235	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T146	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T13	1		T362	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T182	4		T343	1		T289	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T243	16		T263	13		T260	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T129	4		T96	6		T244	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T155	14		T237	11		T255	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T50	5		T155	10		T148	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T229	7		T136	18		T243	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T8	1		T94	1		T238	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T37	10		T126	10		T244	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T130	25		T152	13		T98	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T51	15		T152	3		T233	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T28	2		T96	3		T260	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T101	4		T148	16		T237	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T142	10		T155	11		T231	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T38	11		T232	13		T146	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T93	2		T296	9		T274	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T35	13		T267	1		T159	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T17	1		T50	16		T47	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1406	1			T14	9		T131	16		T146	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9