Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T126	13		T257	9		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T29	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T148	12		T208	10		T258	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T266	12		T246	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T231	14		T241	1		T91	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T51	16		T96	9		T233	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T15	1		T19	1		T21	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T20	1		T132	1		T47	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	4		T17	4		T232	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T133	1		T155	11		T96	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T50	17		T237	6		T267	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T128	1		T129	5		T230	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T174	1		T135	1		T154	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T141	1		T62	2		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T259	1		T96	7		T237	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T132	1		T35	14		T98	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T141	1		T129	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	10		T128	1		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T18	1		T38	12		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T132	1		T206	1		T146	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T13	4		T16	5		T28	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T37	11		T140	1		T130	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T126	9		T257	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T258	5		T268	7		T269	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T266	8		T246	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T91	11		T242	4		T270	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T51	10		T96	10		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T19	10		T21	6		T142	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T152	16		T155	11		T263	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	1		T17	1		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T133	11		T155	12		T96	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T50	18		T237	10		T267	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T129	4		T230	2		T147	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T154	15		T249	6		T271	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T62	1		T126	1		T243	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T96	6		T237	7		T272	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T35	12		T233	1		T93	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T129	1		T135	14		T234	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	11		T247	13		T242	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T176	12		T35	6		T86	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T206	3		T126	9		T94	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T13	1		T16	2		T28	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T37	10		T140	15		T133	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T231	1		T148	1		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T51	11		T132	1		T152	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T15	1		T19	11		T21	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T20	1		T47	1		T152	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	4		T17	4		T155	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T128	1		T129	5		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T50	19		T135	1		T154	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T230	3		T155	13		T147	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T174	1		T259	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T141	1		T132	1		T62	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T141	1		T134	1		T135	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T14	12		T126	2		T233	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T18	1		T129	2		T176	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T132	1		T136	1		T126	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T38	1		T35	7		T86	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T128	1		T206	4		T145	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T13	4		T16	7		T28	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T37	11		T140	16		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T81	1		T133	9		T147	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T260	9		T200	1		T261	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T231	13		T148	11		T260	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T51	15		T152	3		T155	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T142	10		T130	10		T131	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T47	1		T152	13		T263	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	1		T17	1		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T129	4		T96	3		T244	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T50	16		T154	17		T148	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T155	10		T237	11		T260	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T231	13		T249	6		T158	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T62	1		T98	7		T243	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T96	6		T237	7		T273	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	9		T93	2		T252	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T146	32		T86	8		T249	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T136	8		T126	10		T35	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T38	11		T35	6		T86	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T146	2		T136	11		T94	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T13	1		T28	2		T50	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T37	10		T130	15		T163	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T101	4		T274	1		T275	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T260	11		T261	11		T236	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T126	10		T257	4		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T29	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T148	1		T208	1		T258	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T266	9		T246	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T231	1		T241	1		T91	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T51	11		T96	11		T233	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T15	1		T19	11		T21	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T20	1		T132	1		T47	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	4		T17	4		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T133	12		T155	13		T96	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T50	19		T237	11		T267	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T128	1		T129	5		T230	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T174	1		T135	1		T154	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T141	1		T62	2		T126	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T259	1		T96	7		T237	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T132	1		T35	13		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T141	1		T129	2		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	12		T128	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T18	1		T38	1		T176	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T132	1		T206	4		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	431	1			T13	4		T16	7		T28	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T37	11		T140	16		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T126	12		T257	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T148	11		T208	9		T268	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T266	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T231	13		T273	1		T270	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T51	15		T96	8		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T142	10		T130	10		T131	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T47	1		T152	16		T155	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	1		T17	1		T232	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T155	10		T96	3		T244	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T50	16		T237	5		T267	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T129	4		T237	11		T276	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T154	17		T231	13		T148	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T62	1		T243	16		T260	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T96	6		T237	7		T273	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T35	13		T98	7		T93	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T146	13		T249	9		T238	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	9		T136	8		T255	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T38	11		T146	19		T35	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T146	2		T136	11		T126	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T13	1		T28	2		T50	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T37	10		T130	15		T163	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9