Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17356

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

5769

1

T13

5

T14

21

T15

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17118

1

T2

20

T3

20

T4

13

auto[1]

6007

1

T8

5

T13

5

T14

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	43	1			T141	1		T208	11		T277	15
values[0]	134	1			T13	5		T243	27		T184	1
values[1]	620	1			T145	13		T146	3		T147	7
values[2]	636	1			T129	9		T174	1		T176	13
values[3]	874	1			T8	5		T50	11		T229	15
values[4]	431	1			T37	21		T141	1		T132	1
values[5]	660	1			T20	1		T51	26		T129	2
values[6]	727	1			T28	7		T81	1		T132	1
values[7]	783	1			T38	12		T128	1		T142	19
values[8]	568	1			T16	7		T18	1		T206	11
values[9]	3672	1			T14	21		T15	1		T17	5
minimum	13977	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	967	1			T13	5		T145	13		T146	3
values[1]	2991	1			T15	1		T19	11		T21	7
values[2]	656	1			T37	21		T229	15		T126	2
values[3]	563	1			T8	5		T20	1		T141	1
values[4]	698	1			T51	26		T129	2		T130	16
values[5]	730	1			T28	7		T81	1		T132	1
values[6]	622	1			T38	12		T128	1		T142	19
values[7]	607	1			T16	7		T50	35		T140	16
values[8]	1109	1			T14	21		T17	5		T18	1
values[9]	201	1			T134	1		T205	1		T126	22
minimum	13981	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T146	3		T147	1		T234	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T13	4		T145	1		T243	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T50	6		T129	5		T174	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1650	1			T15	1		T19	1		T21	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T94	3		T278	1		T237	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T37	11		T229	8		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	4		T141	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T20	1		T133	1		T126	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T51	16		T130	16		T152	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T129	1		T152	4		T101	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T28	5		T133	1		T155	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T81	1		T132	1		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T142	11		T133	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T38	12		T128	1		T232	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T16	5		T50	17		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T140	1		T132	1		T206	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T17	4		T128	1		T47	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T14	10		T18	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T134	1		T89	4		T208	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T205	1		T126	13		T279	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13880	1			T2	20		T3	20		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T147	6		T242	12		T280	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T13	1		T145	12		T243	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T50	5		T129	4		T155	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	933	1			T19	10		T21	6		T281	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T94	1		T237	7		T238	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T37	10		T229	7		T126	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T8	1		T230	2		T241	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T133	8		T126	9		T147	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T51	10		T152	12		T96	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T129	1		T152	4		T101	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T28	2		T133	11		T155	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T135	10		T239	2		T164	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T142	8		T133	15		T135	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T282	19		T283	12		T284	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T16	2		T50	18		T154	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T140	15		T206	10		T154	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T17	1		T176	12		T147	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T14	11		T144	12		T62	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T89	3		T199	7		T285	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T126	9		T274	16		T286	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T6	1		T16	2		T46	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T208	11		T277	15		T287	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T141	1		T246	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T184	1		T31	2		T288	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T13	4		T243	17		T289	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T146	3		T147	1		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T145	1		T263	14		T241	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T129	5		T174	1		T96	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T176	1		T155	15		T237	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T8	4		T50	6		T155	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T229	8		T133	1		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T141	1		T132	1		T230	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T37	11		T126	11		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T51	16		T130	27		T152	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T20	1		T129	1		T244	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T28	5		T133	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T81	1		T132	1		T152	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T142	11		T133	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T38	12		T128	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T16	5		T134	1		T96	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T18	1		T206	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T17	4		T50	17		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1841	1			T14	10		T15	1		T19	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T246	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T288	5		T290	2		T291	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T13	1		T243	10		T289	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T147	6		T242	12		T280	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T145	12		T263	10		T260	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T129	4		T96	6		T244	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T176	12		T155	11		T237	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	1		T50	5		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T229	7		T133	8		T206	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T230	2		T241	2		T251	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T37	10		T126	9		T147	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T51	10		T152	12		T260	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T129	1		T244	17		T233	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T28	2		T133	11		T96	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T152	4		T101	13		T237	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T142	8		T133	15		T135	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T135	10		T164	16		T282	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T16	2		T96	10		T93	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T206	10		T35	12		T267	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T17	1		T50	18		T176	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1211	1			T14	11		T19	10		T21	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T146	1		T147	7		T234	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T13	4		T145	13		T243	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T50	6		T129	5		T174	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1264	1			T15	1		T19	11		T21	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T94	3		T278	1		T237	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T37	11		T229	8		T126	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	4		T141	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T20	1		T133	9		T126	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T51	11		T130	1		T152	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T129	2		T152	5		T101	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T28	5		T133	12		T155	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T81	1		T132	1		T135	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T142	9		T133	16		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T38	1		T128	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	7		T50	19		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T140	16		T132	1		T206	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T17	4		T128	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T14	12		T18	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T134	1		T89	4		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T205	1		T126	10		T279	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13981	1			T2	20		T3	20		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T146	2		T208	9		T182	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T13	1		T243	16		T263	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T50	5		T129	4		T155	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1319	1			T131	16		T155	14		T136	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T94	1		T237	7		T238	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T37	10		T229	7		T243	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T8	1		T130	10		T98	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T126	10		T244	12		T233	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T51	15		T130	15		T152	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T152	3		T101	4		T237	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T28	2		T155	11		T231	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T146	13		T148	16		T164	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T142	10		T93	2		T247	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T38	11		T232	13		T231	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T50	16		T154	15		T96	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T146	19		T35	13		T267	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T17	1		T47	1		T153	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T14	9		T62	1		T136	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T89	3		T208	10		T199	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T126	12		T274	14		T289	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T208	1		T277	1		T287	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T141	1		T246	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T184	1		T31	2		T288	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T13	4		T243	11		T289	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T146	1		T147	7		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T145	13		T263	11		T241	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T129	5		T174	1		T96	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T176	13		T155	12		T237	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T8	4		T50	6		T155	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T229	8		T133	9		T206	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T141	1		T132	1		T230	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T37	11		T126	10		T147	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T51	11		T130	2		T152	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T20	1		T129	2		T244	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T28	5		T133	12		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T81	1		T132	1		T152	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T142	9		T133	16		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T38	1		T128	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T16	7		T134	1		T96	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T18	1		T206	11		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T17	4		T50	19		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1576	1			T14	12		T15	1		T19	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T208	10		T277	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T291	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T13	1		T243	16		T289	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T146	2		T182	4		T187	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T263	13		T260	16		T292	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T129	4		T96	6		T244	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T155	14		T237	11		T255	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T8	1		T50	5		T155	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T229	7		T136	18		T243	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T238	9		T261	11		T293	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T37	10		T126	10		T294	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T51	15		T130	25		T152	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T244	12		T233	19		T295	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T28	2		T96	3		T249	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T152	3		T101	4		T148	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T142	10		T155	11		T231	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T38	11		T232	13		T146	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T96	8		T93	2		T296	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T136	11		T35	13		T267	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T17	1		T50	16		T47	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1476	1			T14	9		T131	16		T62	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9