Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19452

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3673

1

T13

5

T14

21

T16

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17158

1

T2

20

T3

20

T4

13

auto[1]

5967

1

T8

5

T13

2

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	335	1			T13	2		T16	1		T58	1
values[0]	31	1			T8	5		T297	17		T298	9
values[1]	678	1			T140	16		T146	23		T259	1
values[2]	2787	1			T15	1		T18	1		T19	11
values[3]	818	1			T16	7		T50	35		T132	1
values[4]	594	1			T14	21		T38	12		T152	8
values[5]	738	1			T17	5		T129	2		T133	16
values[6]	931	1			T28	7		T81	1		T51	26
values[7]	543	1			T37	21		T141	1		T130	11
values[8]	730	1			T13	5		T50	11		T134	2
values[9]	1271	1			T20	1		T128	1		T132	1
minimum	13669	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	926	1			T140	16		T144	13		T146	23
values[1]	2779	1			T15	1		T16	7		T18	1
values[2]	722	1			T14	21		T132	1		T47	2
values[3]	666	1			T38	12		T152	8		T137	4
values[4]	856	1			T28	7		T51	26		T129	9
values[5]	692	1			T17	5		T81	1		T141	1
values[6]	602	1			T37	21		T132	1		T130	11
values[7]	837	1			T13	5		T50	11		T229	15
values[8]	846	1			T20	1		T128	1		T132	1
values[9]	211	1			T243	27		T299	27		T161	8
minimum	13988	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T140	1		T146	23		T98	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T144	1		T259	1		T126	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1507	1			T15	1		T18	1		T19	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T16	5		T50	17		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T47	2		T152	14		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	10		T132	1		T153	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T152	4		T137	4		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T38	12		T154	16		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T51	16		T133	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T28	5		T129	5		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T17	4		T129	1		T142	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T81	1		T141	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T37	11		T130	11		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T132	1		T279	1		T278	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T50	6		T134	1		T155	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	4		T229	8		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T20	1		T132	1		T136	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T128	1		T230	1		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T300	8		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T243	17		T299	14		T161	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13886	1			T2	20		T3	20		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T140	15		T263	10		T301	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T144	12		T126	9		T147	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	904	1			T19	10		T21	6		T281	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T16	2		T50	18		T302	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T152	12		T145	12		T239	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	11		T260	4		T233	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T152	4		T147	4		T154	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T154	12		T242	12		T182	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T51	10		T133	15		T135	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T28	2		T129	4		T155	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T17	1		T129	1		T142	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T133	8		T303	29		T240	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T37	10		T133	11		T206	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T239	10		T238	7		T235	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T50	5		T155	12		T154	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	1		T229	7		T96	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T241	2		T164	7		T251	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T230	2		T176	12		T155	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T300	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T243	10		T299	13		T161	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T6	1		T8	1		T16	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T13	2		T16	1		T58	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T299	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T8	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T297	9		T298	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T140	1		T146	23		T98	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T259	1		T126	13		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1574	1			T15	1		T18	1		T19	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T128	1		T144	1		T153	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T47	2		T152	14		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T16	5		T50	17		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T152	4		T137	4		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	10		T38	12		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T17	4		T129	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T174	1		T154	16		T148	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T51	16		T142	11		T206	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T28	5		T81	1		T129	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T37	11		T130	11		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T141	1		T133	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T50	6		T134	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	4		T134	1		T205	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T20	1		T132	1		T155	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	468	1			T128	1		T229	8		T230	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13570	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T299	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T8	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T297	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T140	15		T263	10		T280	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T126	9		T147	2		T244	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T19	10		T21	6		T281	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T144	12		T302	5		T164	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T152	12		T145	12		T126	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T16	2		T50	18		T260	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T152	4		T147	4		T304	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	11		T233	11		T91	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T17	1		T129	1		T133	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T154	12		T267	1		T244	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T51	10		T142	8		T206	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T28	2		T129	4		T155	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T37	10		T133	11		T206	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T133	8		T239	10		T238	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T50	5		T154	1		T35	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	1		T96	10		T305	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T155	12		T237	7		T241	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	386	1			T229	7		T230	2		T176	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T140	16		T146	2		T98	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T144	13		T259	1		T126	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T15	1		T18	1		T19	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T16	7		T50	19		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T47	1		T152	13		T145	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T14	12		T132	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T152	5		T137	4		T147	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T38	1		T154	13		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T51	11		T133	16		T135	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T28	5		T129	5		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T17	4		T129	2		T142	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T81	1		T141	1		T133	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T37	11		T130	1		T133	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T132	1		T279	1		T278	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T50	6		T134	1		T155	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	4		T229	8		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T20	1		T132	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T128	1		T230	3		T176	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T300	3		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T243	11		T299	14		T161	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13986	1			T2	20		T3	20		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T146	21		T98	7		T263	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T126	12		T244	12		T182	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T131	16		T253	12		T94	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T50	16		T130	15		T164	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T47	1		T152	13		T136	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	9		T153	10		T260	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T152	3		T154	17		T231	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T38	11		T154	15		T295	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T51	15		T62	1		T126	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T28	2		T129	4		T155	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T17	1		T142	10		T146	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T303	23		T240	16		T235	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	10		T130	10		T232	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T238	5		T235	7		T274	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T50	5		T155	11		T231	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	1		T229	7		T96	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T136	11		T148	16		T164	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T155	14		T136	18		T243	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T300	7		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T243	16		T299	13		T161	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T8	1		T306	1		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T13	2		T16	1		T58	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T299	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T8	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T297	9		T298	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T140	16		T146	2		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T259	1		T126	10		T147	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T15	1		T18	1		T19	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T128	1		T144	13		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T47	1		T152	13		T145	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T16	7		T50	19		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T152	5		T137	4		T147	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	12		T38	1		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T17	4		T129	2		T133	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T174	1		T154	13		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T51	11		T142	9		T206	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T28	5		T81	1		T129	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T37	11		T130	1		T133	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T141	1		T133	9		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T50	6		T134	1		T154	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	4		T134	1		T205	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T20	1		T132	1		T155	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	448	1			T128	1		T229	8		T230	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13669	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T299	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T8	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T297	8		T298	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T146	21		T98	7		T263	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T126	12		T244	12		T245	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T131	16		T253	12		T102	36
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T153	10		T164	20		T182	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T47	1		T152	13		T136	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T50	16		T130	15		T260	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T152	3		T255	15		T304	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	9		T38	11		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T17	1		T62	1		T126	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T154	15		T148	2		T267	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T51	15		T142	10		T146	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T28	2		T129	4		T155	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T37	10		T130	10		T232	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T238	5		T273	14		T307	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T50	5		T35	6		T101	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	1		T96	8		T305	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T155	11		T136	11		T231	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T229	7		T155	14		T136	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9