Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19519

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3606

1

T8

5

T13

5

T16

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16919

1

T2

20

T3

20

T4

13

auto[1]

6206

1

T13

5

T14

21

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T308	28		-	-		-	-
values[0]	98	1			T96	13		T304	16		T86	19
values[1]	835	1			T16	7		T152	8		T133	16
values[2]	744	1			T51	26		T136	9		T147	5
values[3]	737	1			T17	5		T20	1		T141	1
values[4]	642	1			T13	5		T129	2		T144	13
values[5]	2796	1			T15	1		T19	11		T21	7
values[6]	702	1			T37	21		T50	35		T132	2
values[7]	880	1			T14	21		T81	1		T140	16
values[8]	601	1			T130	11		T153	11		T259	1
values[9]	1085	1			T8	5		T18	1		T38	12
minimum	13977	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1139	1			T152	8		T133	16		T205	1
values[1]	648	1			T16	7		T17	5		T20	1
values[2]	790	1			T129	2		T48	1		T134	1
values[3]	2895	1			T13	5		T15	1		T19	11
values[4]	590	1			T37	21		T141	1		T142	19
values[5]	683	1			T50	35		T140	16		T132	1
values[6]	819	1			T14	21		T81	1		T152	26
values[7]	670	1			T38	12		T47	2		T130	11
values[8]	720	1			T8	5		T28	7		T50	11
values[9]	186	1			T18	1		T309	12		T310	20
minimum	13985	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T152	4		T137	4		T147	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T133	1		T205	1		T146	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T20	1		T141	1		T129	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T16	5		T17	4		T51	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T129	1		T134	1		T155	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T48	1		T148	3		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1585	1			T15	1		T19	1		T21	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	4		T144	1		T176	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T141	1		T132	1		T130	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T37	11		T142	11		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	1		T176	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T50	17		T140	1		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T14	10		T152	14		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T81	1		T154	16		T267	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T38	12		T47	2		T130	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T229	8		T126	11		T96	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T28	5		T50	6		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	4		T128	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T242	1		T277	13		T266	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T18	1		T309	1		T310	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13879	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T147	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T152	4		T147	6		T35	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T133	15		T243	12		T304	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T129	4		T251	12		T238	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T16	2		T17	1		T51	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T129	1		T155	11		T241	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T260	10		T93	4		T311	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	925	1			T19	10		T21	6		T281	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	1		T144	12		T176	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T237	5		T280	2		T312	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T37	10		T142	8		T133	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T176	12		T135	10		T101	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T50	18		T140	15		T237	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	11		T152	12		T133	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T154	12		T267	1		T91	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T154	1		T244	17		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T229	7		T126	9		T96	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T28	2		T50	5		T302	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	1		T230	2		T206	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T242	8		T266	16		T313	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T309	11		T310	9		T314	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T147	6		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T308	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T96	7		T86	9		T315	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T304	10		T294	2		T315	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T152	4		T137	4		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T16	5		T133	1		T205	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T147	1		T251	1		T238	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T51	16		T136	9		T231	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T20	1		T141	1		T129	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T17	4		T48	1		T148	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T129	1		T130	16		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	4		T144	1		T176	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1562	1			T15	1		T19	1		T21	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T142	11		T133	1		T232	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T132	2		T206	1		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T37	11		T50	17		T174	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T14	10		T152	14		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T81	1		T140	1		T267	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T130	11		T153	11		T259	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T126	11		T154	16		T96	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T38	12		T28	5		T50	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T8	4		T18	1		T128	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T308	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T96	6		T86	10		T315	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T304	6		T294	1		T315	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T152	4		T147	2		T35	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T16	2		T133	15		T147	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T147	4		T251	12		T238	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T51	10		T233	1		T311	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T129	4		T155	11		T241	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T17	1		T280	11		T235	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T129	1		T238	7		T305	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	1		T144	12		T176	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T19	10		T21	6		T281	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T142	8		T133	8		T135	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T206	3		T176	12		T237	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T37	10		T50	18		T237	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T14	11		T152	12		T133	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T140	15		T267	1		T91	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T154	1		T244	17		T233	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T126	9		T154	12		T96	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T28	2		T50	5		T302	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	1		T229	7		T230	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T152	5		T137	4		T147	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T133	16		T205	1		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T20	1		T141	1		T129	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	7		T17	4		T51	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T129	2		T134	1		T155	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T48	1		T148	1		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T15	1		T19	11		T21	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	4		T144	13		T176	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T141	1		T132	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T37	11		T142	9		T133	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T132	1		T176	13		T135	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T50	19		T140	16		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T14	12		T152	13		T133	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T81	1		T154	13		T267	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T38	1		T47	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T229	8		T126	10		T96	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T28	5		T50	6		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	4		T128	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T242	9		T277	1		T266	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T18	1		T309	12		T310	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13978	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T147	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T152	3		T35	6		T94	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T146	2		T136	18		T231	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T129	4		T238	14		T256	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T17	1		T51	15		T136	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T155	14		T136	11		T292	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T148	2		T260	16		T93	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T131	16		T253	12		T102	36
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	1		T126	12		T154	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T130	15		T146	19		T237	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T37	10		T142	10		T232	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T231	13		T101	4		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T50	16		T148	5		T237	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	9		T152	13		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T154	15		T267	1		T240	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T38	11		T47	1		T130	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T229	7		T126	10		T96	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T28	2		T50	5		T260	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	1		T155	11		T146	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T277	12		T266	7		T313	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T310	10		T316	11		T317	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T308	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T96	7		T86	11		T315	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T304	7		T294	2		T315	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T152	5		T137	4		T147	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T16	7		T133	16		T205	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T147	5		T251	13		T238	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T51	11		T136	1		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T20	1		T141	1		T129	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T17	4		T48	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T129	2		T130	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	4		T144	13		T176	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T15	1		T19	11		T21	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T142	9		T133	9		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T132	2		T206	4		T176	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T37	11		T50	19		T174	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T14	12		T152	13		T133	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T81	1		T140	16		T267	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T130	1		T153	1		T259	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T126	10		T154	13		T96	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T38	1		T28	5		T50	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T8	4		T18	1		T128	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T308	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T96	6		T86	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T304	9		T294	1		T318	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T152	3		T35	6		T94	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T146	2		T136	18		T243	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T238	14		T256	9		T270	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T51	15		T136	8		T231	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T129	4		T155	14		T136	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T17	1		T148	2		T273	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T130	15		T238	5		T305	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	1		T154	17		T98	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T131	16		T253	12		T102	36
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T142	10		T232	13		T62	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T146	19		T231	13		T237	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T37	10		T50	16		T148	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	9		T152	13		T155	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T267	1		T240	16		T158	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T130	10		T153	10		T244	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T126	10		T154	15		T96	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T38	11		T28	2		T50	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T8	1		T229	7		T155	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9