Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19601

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3524

1

T8

5

T16

7

T18

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17042

1

T2

20

T3

20

T4

13

auto[1]

6083

1

T8

5

T13

5

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	25	1			T282	14		T319	10		T320	1
values[0]	89	1			T48	1		T146	20		T233	23
values[1]	762	1			T37	21		T28	7		T229	15
values[2]	708	1			T17	5		T128	1		T176	13
values[3]	697	1			T14	21		T129	9		T230	3
values[4]	488	1			T8	5		T18	1		T50	11
values[5]	709	1			T13	5		T20	1		T130	16
values[6]	734	1			T50	35		T81	1		T133	16
values[7]	570	1			T128	1		T141	1		T51	26
values[8]	701	1			T16	7		T38	12		T140	16
values[9]	3665	1			T15	1		T19	11		T21	7
minimum	13977	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1051	1			T37	21		T128	1		T229	15
values[1]	660	1			T14	21		T17	5		T28	7
values[2]	707	1			T129	11		T155	26		T126	2
values[3]	486	1			T8	5		T13	5		T18	1
values[4]	682	1			T141	1		T132	1		T232	14
values[5]	732	1			T50	35		T81	1		T47	2
values[6]	3043	1			T15	1		T19	11		T21	7
values[7]	483	1			T16	7		T140	16		T132	1
values[8]	1054	1			T132	1		T144	13		T130	11
values[9]	249	1			T147	5		T279	1		T148	3
minimum	13978	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T37	11		T128	1		T48	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T229	8		T134	1		T136	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	10		T17	4		T28	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T153	11		T155	12		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T129	5		T155	15		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T129	1		T35	7		T276	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T13	4		T50	6		T152	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	4		T18	1		T20	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T141	1		T232	14		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T132	1		T145	1		T146	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T133	1		T96	4		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T50	17		T81	1		T47	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1734	1			T15	1		T19	1		T21	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T128	1		T135	1		T126	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T140	1		T133	1		T62	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T16	5		T132	1		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T130	11		T133	1		T259	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T132	1		T144	1		T152	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T147	1		T279	1		T148	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T208	11		T227	20		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T321	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	10		T154	15		T263	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T229	7		T241	2		T86	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	11		T17	1		T28	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T155	12		T147	2		T154	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T129	4		T155	11		T126	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T129	1		T35	6		T89	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T13	1		T50	5		T152	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T8	1		T206	13		T267	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T155	12		T238	7		T199	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T145	12		T243	22		T233	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T133	15		T96	3		T260	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T50	18		T35	12		T244	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T19	10		T21	6		T51	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T135	14		T126	9		T233	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T140	15		T133	8		T62	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T16	2		T237	7		T234	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T133	11		T96	10		T302	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T144	12		T152	12		T135	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T147	4		T199	12		T282	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T227	15		T271	2		T322	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T282	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T319	10		T320	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T48	1		T146	20		T233	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T277	12		T323	1		T324	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T37	11		T28	5		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T229	8		T134	1		T136	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T17	4		T128	1		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T148	12		T276	2		T242	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	10		T129	5		T230	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T153	11		T155	12		T154	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T50	6		T141	1		T152	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	4		T18	1		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	4		T232	14		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T20	1		T130	16		T206	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T133	1		T176	1		T96	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T50	17		T81	1		T231	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T141	1		T51	16		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T128	1		T47	2		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T38	12		T140	1		T142	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	5		T152	14		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1817	1			T15	1		T19	1		T21	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T132	2		T144	1		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T282	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T233	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T323	1		T324	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	10		T28	2		T240	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T229	7		T147	2		T241	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T17	1		T176	12		T154	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T242	8		T248	7		T184	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	11		T129	4		T230	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T155	12		T154	12		T35	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T50	5		T152	4		T126	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	1		T129	1		T206	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	1		T155	12		T126	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T206	10		T145	12		T267	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T133	15		T176	12		T96	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T50	18		T35	12		T243	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T51	10		T96	6		T262	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T126	9		T233	2		T303	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T140	15		T142	8		T133	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T16	2		T152	12		T135	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1074	1			T19	10		T21	6		T281	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T144	12		T135	10		T94	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T37	11		T128	1		T48	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T229	8		T134	1		T136	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	12		T17	4		T28	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T153	1		T155	13		T147	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T129	5		T155	12		T126	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T129	2		T35	7		T276	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T13	4		T50	6		T152	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	4		T18	1		T20	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T141	1		T232	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T132	1		T145	13		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T133	16		T96	4		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T50	19		T81	1		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T15	1		T19	11		T21	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T128	1		T135	15		T126	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T140	16		T133	9		T62	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T16	7		T132	1		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T130	1		T133	12		T259	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T132	1		T144	13		T152	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T147	5		T279	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T208	1		T227	16		T271	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T321	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T37	10		T146	19		T154	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T229	7		T136	26		T86	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	9		T17	1		T28	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T153	10		T155	11		T154	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T129	4		T155	14		T260	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T35	6		T276	6		T89	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T13	1		T50	5		T152	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T8	1		T130	15		T267	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T232	13		T155	10		T238	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T146	13		T231	13		T243	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T96	3		T260	11		T249	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T50	16		T47	1		T35	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T38	11		T51	15		T142	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T126	10		T233	8		T323	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T62	1		T96	6		T101	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T237	7		T295	14		T311	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T130	10		T96	8		T164	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T152	13		T94	1		T260	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T148	2		T255	15		T296	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T208	10		T227	19		T325	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T282	14		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T319	1		T320	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T48	1		T146	1		T233	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T277	1		T323	2		T324	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T37	11		T28	5		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T229	8		T134	1		T136	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T17	4		T128	1		T176	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T148	1		T276	1		T242	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	12		T129	5		T230	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T153	1		T155	13		T154	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T50	6		T141	1		T152	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	4		T18	1		T129	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	4		T232	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T20	1		T130	1		T206	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T133	16		T176	13		T96	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T50	19		T81	1		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T141	1		T51	11		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T128	1		T47	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T38	1		T140	16		T142	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T16	7		T152	13		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1439	1			T15	1		T19	11		T21	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	449	1			T132	2		T144	13		T135	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T319	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T146	19		T233	11		T326	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T277	11		T324	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T37	10		T28	2		T240	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T229	7		T136	26		T86	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T17	1		T154	17		T237	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T148	11		T276	1		T184	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	9		T129	4		T155	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T153	10		T155	11		T154	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T50	5		T152	3		T249	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T8	1		T243	7		T276	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	1		T232	13		T155	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T130	15		T146	13		T267	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T96	3		T260	11		T249	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T50	16		T231	13		T35	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T51	15		T146	2		T136	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T47	1		T126	10		T148	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T38	11		T142	10		T62	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T152	13		T237	7		T295	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1452	1			T130	10		T131	16		T253	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T94	1		T260	5		T292	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9