Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19764

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3361

1

T14

21

T18

1

T37

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16805

1

T2

20

T3

20

T4

13

auto[1]

6320

1

T13

5

T14

21

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	340	1			T232	14		T231	14		T96	13
values[0]	3	1			T327	1		T202	1		T328	1
values[1]	566	1			T14	21		T38	12		T141	1
values[2]	557	1			T128	1		T141	1		T51	26
values[3]	620	1			T17	5		T129	9		T229	15
values[4]	654	1			T16	7		T142	19		T130	11
values[5]	2999	1			T15	1		T19	11		T21	7
values[6]	979	1			T8	5		T13	5		T132	1
values[7]	625	1			T18	1		T37	21		T128	1
values[8]	720	1			T20	1		T28	7		T50	11
values[9]	1085	1			T50	35		T133	37		T176	13
minimum	13977	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	483	1			T38	12		T141	1		T132	2
values[1]	574	1			T128	1		T141	1		T51	26
values[2]	539	1			T17	5		T129	9		T135	11
values[3]	2990	1			T15	1		T16	7		T19	11
values[4]	769	1			T144	13		T134	1		T146	23
values[5]	909	1			T8	5		T13	5		T129	2
values[6]	584	1			T18	1		T37	21		T128	1
values[7]	787	1			T20	1		T28	7		T50	11
values[8]	1098	1			T50	35		T133	28		T232	14
values[9]	151	1			T231	14		T263	24		T241	1
minimum	14241	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T141	1		T132	2		T154	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T38	12		T94	3		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T128	1		T259	1		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T141	1		T51	16		T47	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T17	4		T136	12		T233	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T129	5		T135	1		T255	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1698	1			T15	1		T16	5		T19	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T243	8		T162	1		T86	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T134	1		T146	20		T136	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T144	1		T146	3		T137	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	4		T13	4		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T152	4		T205	1		T146	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T206	1		T147	1		T148	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T18	1		T37	11		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T20	1		T28	5		T50	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T81	1		T140	1		T152	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T50	17		T133	1		T232	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T133	1		T155	11		T62	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T231	14		T263	14		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T158	11		T282	1		T329	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13921	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T14	10		T206	1		T98	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T154	12		T302	5		T260	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T94	1		T244	17		T91	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T126	1		T147	4		T243	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T51	10		T229	7		T155	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T17	1		T233	11		T239	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T129	4		T135	10		T244	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T16	2		T19	10		T21	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T243	12		T86	10		T249	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T251	12		T280	11		T301	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T144	12		T154	1		T35	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	1		T13	1		T129	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T152	4		T126	9		T96	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T206	3		T147	2		T260	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T37	10		T96	3		T241	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T28	2		T50	5		T126	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T140	15		T152	12		T133	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T50	18		T133	15		T176	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T133	11		T155	12		T62	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T263	10		T89	3		T330	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T158	12		T282	10		T300	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T16	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T14	11		T206	10		T199	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T232	14		T231	14		T99	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T96	7		T278	1		T240	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T327	1		T202	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T328	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T141	1		T132	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	10		T38	12		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T128	1		T132	1		T259	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T141	1		T51	16		T47	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	4		T136	12		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T129	5		T229	8		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T16	5		T142	11		T130	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T135	1		T243	8		T244	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1712	1			T15	1		T19	1		T21	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T144	1		T146	3		T137	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T8	4		T13	4		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T152	4		T205	1		T146	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T129	1		T206	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T18	1		T37	11		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T20	1		T28	5		T50	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T81	1		T140	1		T292	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T50	17		T133	1		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T133	2		T155	11		T62	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T330	1		T331	4		T315	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T96	6		T240	15		T280	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T154	12		T302	5		T260	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	11		T206	10		T94	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T126	1		T243	10		T262	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T51	10		T147	6		T237	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T17	1		T147	4		T233	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T129	4		T229	7		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T16	2		T142	8		T237	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T135	10		T243	12		T244	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	945	1			T19	10		T21	6		T281	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T144	12		T154	1		T35	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	1		T13	1		T230	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T152	4		T126	9		T96	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T129	1		T206	3		T147	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T37	10		T152	12		T96	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T28	2		T50	5		T154	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T140	15		T292	11		T238	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T50	18		T133	15		T176	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T133	19		T155	12		T62	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T141	1		T132	2		T154	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T38	1		T94	3		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T128	1		T259	1		T126	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T141	1		T51	11		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T17	4		T136	1		T233	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T129	5		T135	11		T255	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T15	1		T16	7		T19	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T243	13		T162	1		T86	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T134	1		T146	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T144	13		T146	1		T137	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T8	4		T13	4		T129	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T152	5		T205	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T206	4		T147	3		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T18	1		T37	11		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T20	1		T28	5		T50	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T81	1		T140	16		T152	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T50	19		T133	16		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T133	12		T155	13		T62	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T231	1		T263	11		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T158	13		T282	11		T329	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14018	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T14	12		T206	11		T98	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T154	15		T260	11		T240	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T38	11		T94	1		T244	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T231	13		T243	16		T254	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T51	15		T47	1		T229	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T17	1		T136	11		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T129	4		T255	15		T244	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T142	10		T130	10		T131	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T243	7		T86	8		T249	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T146	19		T136	18		T163	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T146	2		T35	6		T101	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	1		T13	1		T260	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T152	3		T146	13		T126	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T148	5		T260	5		T304	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T37	10		T130	15		T96	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T28	2		T50	5		T136	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T152	13		T292	11		T238	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T50	16		T232	13		T155	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T155	10		T62	1		T96	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T231	13		T263	13		T89	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T158	10		T329	6		T300	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T329	12		T178	6		T298	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T14	9		T98	7		T199	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T232	1		T231	1		T99	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T96	7		T278	1		T240	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T327	1		T202	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T328	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T141	1		T132	1		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	12		T38	1		T206	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T128	1		T132	1		T259	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T141	1		T51	11		T47	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T17	4		T136	1		T147	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T129	5		T229	8		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T16	7		T142	9		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T135	11		T243	13		T244	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T15	1		T19	11		T21	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T144	13		T146	1		T137	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T8	4		T13	4		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T152	5		T205	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T129	2		T206	4		T147	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T18	1		T37	11		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T20	1		T28	5		T50	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T81	1		T140	16		T292	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T50	19		T133	16		T176	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T133	21		T155	13		T62	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T232	13		T231	13		T332	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T96	6		T240	8		T158	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T154	15		T260	11		T240	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	9		T38	11		T94	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T231	13		T243	16		T182	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T51	15		T47	1		T237	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T17	1		T136	11		T233	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T129	4		T229	7		T155	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T142	10		T130	10		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T243	7		T244	4		T247	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T131	16		T146	19		T136	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T146	2		T35	6		T101	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T8	1		T13	1		T260	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T152	3		T146	13		T126	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T148	5		T260	5		T304	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T37	10		T130	15		T152	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T28	2		T50	5		T154	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T292	11		T238	14		T333	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T50	16		T155	14		T136	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T155	10		T62	1		T148	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9