Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19724

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3401

1

T14

21

T38

12

T50

35

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16901

1

T2

20

T3

20

T4

13

auto[1]

6224

1

T8

5

T13

2

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	530	1			T13	2		T16	1		T58	1
values[0]	58	1			T8	5		T263	24		T280	3
values[1]	672	1			T140	16		T146	23		T259	1
values[2]	2797	1			T15	1		T18	1		T19	11
values[3]	718	1			T16	7		T50	35		T132	1
values[4]	675	1			T14	21		T38	12		T152	34
values[5]	746	1			T51	26		T133	16		T174	1
values[6]	886	1			T17	5		T28	7		T81	1
values[7]	532	1			T37	21		T141	1		T132	1
values[8]	784	1			T13	5		T50	11		T232	14
values[9]	1058	1			T20	1		T128	1		T132	1
minimum	13669	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	744	1			T8	5		T140	16		T144	13
values[1]	2778	1			T15	1		T16	7		T18	1
values[2]	678	1			T132	1		T47	2		T152	26
values[3]	735	1			T14	21		T38	12		T152	8
values[4]	828	1			T28	7		T51	26		T133	16
values[5]	701	1			T17	5		T81	1		T141	1
values[6]	579	1			T37	21		T132	1		T130	11
values[7]	815	1			T13	5		T50	11		T132	1
values[8]	974	1			T20	1		T128	1		T229	15
values[9]	116	1			T299	27		T334	9		T326	12
minimum	14177	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T8	4		T146	23		T276	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T140	1		T144	1		T259	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1528	1			T15	1		T16	5		T18	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T50	17		T128	1		T153	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T47	2		T152	14		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T132	1		T241	1		T260	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T152	4		T137	4		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T14	10		T38	12		T154	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T28	5		T51	16		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T133	1		T174	1		T155	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T17	4		T133	1		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T81	1		T141	1		T129	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T37	11		T130	11		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T132	1		T176	1		T279	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T13	4		T50	6		T134	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T132	1		T205	1		T96	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T20	1		T155	12		T136	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T128	1		T229	8		T230	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T202	1		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T299	14		T334	9		T326	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13934	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T126	13		T147	1		T244	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	1		T301	1		T312	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T140	15		T144	12		T234	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	911	1			T16	2		T19	10		T21	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T50	18		T94	1		T302	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T152	12		T145	12		T247	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T260	4		T233	11		T239	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T152	4		T147	4		T154	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T14	11		T154	12		T199	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T28	2		T51	10		T135	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T133	15		T155	12		T244	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	1		T133	8		T206	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T129	5		T142	8		T294	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T37	10		T133	11		T206	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T176	12		T96	3		T239	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	1		T50	5		T35	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T96	10		T292	11		T305	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T155	12		T243	22		T237	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T229	7		T230	2		T176	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T299	13		T335	11		T336	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T16	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T126	9		T147	2		T244	17

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T13	2		T16	1		T58	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T136	12		T251	1		T327	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T8	4		T263	14		T280	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T297	9		T298	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T146	23		T98	8		T276	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T140	1		T259	1		T126	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1564	1			T15	1		T18	1		T19	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T128	1		T144	1		T153	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T16	5		T47	2		T130	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T50	17		T132	1		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T152	18		T137	4		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	10		T38	12		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T51	16		T62	2		T126	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T133	1		T174	1		T154	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T17	4		T28	5		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T81	1		T129	6		T142	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T37	11		T130	11		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T141	1		T132	1		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T13	4		T50	6		T232	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T205	1		T279	1		T96	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T20	1		T155	12		T136	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T128	1		T132	1		T229	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13570	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T243	10		T272	2		T337	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T251	12		T338	11		T339	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T8	1		T263	10		T280	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T297	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T301	1		T199	4		T159	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T140	15		T126	9		T147	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T19	10		T21	6		T281	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T144	12		T94	1		T302	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T16	2		T145	12		T126	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T50	18		T260	4		T239	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T152	16		T147	4		T304	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T14	11		T233	11		T91	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T51	10		T62	1		T126	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T133	15		T154	12		T244	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T17	1		T28	2		T133	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T129	5		T142	8		T155	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T37	10		T133	11		T206	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T176	12		T96	3		T239	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	1		T50	5		T154	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T96	10		T292	11		T305	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T155	12		T243	12		T237	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T229	7		T230	2		T176	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	4		T146	2		T276	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T140	16		T144	13		T259	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T15	1		T16	7		T18	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T50	19		T128	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T152	13		T145	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T132	1		T241	1		T260	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T152	5		T137	4		T147	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	12		T38	1		T154	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T28	5		T51	11		T135	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T133	16		T174	1		T155	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T17	4		T133	9		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T81	1		T141	1		T129	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T37	11		T130	1		T133	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T132	1		T176	13		T279	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	4		T50	6		T134	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T132	1		T205	1		T96	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T20	1		T155	13		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T128	1		T229	8		T230	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T202	1		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T299	14		T334	1		T326	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14035	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T126	10		T147	3		T244	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	1		T146	21		T276	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T182	5		T334	4		T245	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T130	15		T131	16		T253	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T50	16		T153	10		T94	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T47	1		T152	13		T136	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T260	5		T233	11		T270	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T152	3		T154	17		T231	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	9		T38	11		T154	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T28	2		T51	15		T62	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T155	10		T244	4		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T17	1		T35	13		T260	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T129	4		T142	10		T146	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T37	10		T130	10		T232	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T96	3		T238	5		T274	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	1		T50	5		T231	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T96	8		T292	11		T305	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T155	11		T136	18		T148	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T229	7		T155	14		T136	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T299	13		T334	8		T326	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T98	7		T263	13		T265	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T126	12		T244	12		T298	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T13	2		T16	1		T58	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T136	1		T251	13		T327	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T8	4		T263	11		T280	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T297	9		T298	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T146	2		T98	1		T276	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T140	16		T259	1		T126	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T15	1		T18	1		T19	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T128	1		T144	13		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T16	7		T47	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T50	19		T132	1		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T152	18		T137	4		T147	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	12		T38	1		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T51	11		T62	2		T126	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T133	16		T174	1		T154	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T17	4		T28	5		T133	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T81	1		T129	7		T142	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T37	11		T130	1		T133	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T141	1		T132	1		T176	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	4		T50	6		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T205	1		T279	1		T96	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T20	1		T155	13		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T128	1		T132	1		T229	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13669	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T243	16		T288	12		T340	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T136	11		T333	15		T338	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T8	1		T263	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T297	8		T298	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T146	21		T98	7		T276	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T126	12		T244	12		T245	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T131	16		T253	12		T102	36
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T153	10		T94	1		T164	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T47	1		T130	15		T136	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T50	16		T260	5		T270	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T152	16		T255	15		T304	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	9		T38	11		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T51	15		T62	1		T126	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T154	15		T244	4		T233	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T17	1		T28	2		T267	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T129	4		T142	10		T155	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T37	10		T130	10		T35	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T96	3		T238	5		T273	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	1		T50	5		T232	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T96	8		T292	11		T305	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T155	11		T136	18		T148	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T229	7		T155	14		T86	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9