Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23125

1

T2

20

T3

20

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19742

1

T2

20

T3

20

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3383

1

T8

5

T13

5

T16

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17064

1

T2

20

T3

20

T4

13

auto[1]

6061

1

T13

5

T14

21

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19113

1

T2

20

T3

20

T4

13

auto[1]

4012

1

T6

1

T8

1

T13

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	243	1			T8	5		T18	1		T162	1
values[0]	35	1			T315	15		T318	20		-	-
values[1]	996	1			T152	8		T133	16		T205	1
values[2]	642	1			T16	7		T51	26		T136	9
values[3]	711	1			T17	5		T20	1		T141	1
values[4]	691	1			T13	5		T129	2		T144	13
values[5]	2783	1			T15	1		T19	11		T21	7
values[6]	703	1			T37	21		T50	35		T142	19
values[7]	831	1			T14	21		T81	1		T140	16
values[8]	628	1			T47	2		T130	11		T153	11
values[9]	885	1			T38	12		T28	7		T50	11
minimum	13977	1			T2	20		T3	20		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	877	1			T152	8		T133	16		T205	1
values[1]	665	1			T16	7		T17	5		T141	1
values[2]	754	1			T20	1		T129	2		T48	1
values[3]	2940	1			T13	5		T15	1		T19	11
values[4]	577	1			T37	21		T141	1		T142	19
values[5]	698	1			T50	35		T140	16		T132	1
values[6]	813	1			T14	21		T81	1		T152	26
values[7]	649	1			T38	12		T47	2		T130	11
values[8]	761	1			T8	5		T28	7		T50	11
values[9]	144	1			T18	1		T309	12		T310	20
minimum	14247	1			T2	20		T3	20		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

4257

1

T8

1

T13

1

T14

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T152	4		T137	4		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T133	1		T205	1		T136	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T141	1		T129	5		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T16	5		T17	4		T51	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T20	1		T129	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T48	1		T148	3		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T15	1		T19	1		T21	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	4		T128	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T141	1		T132	1		T135	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T37	11		T142	11		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T132	1		T206	1		T176	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T50	17		T140	1		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T14	10		T152	14		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T81	1		T154	16		T267	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T38	12		T47	2		T229	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T130	11		T153	11		T96	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T28	5		T50	6		T206	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	4		T128	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T310	11		T242	1		T313	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T18	1		T309	1		T316	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13983	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T147	1		T35	7		T243	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T152	4		T147	4		T94	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T133	15		T304	6		T164	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T129	4		T251	12		T238	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T16	2		T17	1		T51	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T129	1		T155	11		T241	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T93	4		T272	16		T311	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T19	10		T21	6		T281	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	1		T144	12		T176	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T135	10		T62	1		T237	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T37	10		T142	8		T133	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T206	3		T176	12		T101	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T50	18		T140	15		T237	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	11		T152	12		T133	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T154	12		T267	1		T91	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T229	7		T126	9		T154	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T96	3		T89	3		T242	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T28	2		T50	5		T206	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T8	1		T230	2		T155	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T310	9		T242	8		T313	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T309	11		T314	2		T341	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	1		T16	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T147	6		T35	6		T243	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T162	1		T157	1		T242	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T8	4		T18	1		T309	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T315	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T318	20		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T152	4		T146	3		T137	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T133	1		T205	1		T136	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T147	1		T251	1		T238	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T16	5		T51	16		T136	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T20	1		T141	1		T129	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T17	4		T48	1		T148	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T129	1		T130	16		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	4		T144	1		T176	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T15	1		T19	1		T21	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T128	1		T133	1		T232	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T132	2		T206	1		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T37	11		T50	17		T142	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T14	10		T152	14		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T81	1		T140	1		T267	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T47	2		T126	11		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T130	11		T153	11		T154	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T38	12		T28	5		T50	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T128	1		T132	1		T230	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13878	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T242	8		T248	7		T342	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T8	1		T309	11		T86	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T315	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T152	4		T147	2		T94	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T133	15		T147	6		T35	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T147	4		T251	12		T238	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T16	2		T51	10		T233	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T129	4		T155	11		T241	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T17	1		T272	16		T311	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T129	1		T237	7		T260	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	1		T144	12		T176	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	938	1			T19	10		T21	6		T281	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T133	8		T135	14		T145	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T206	3		T176	12		T101	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T37	10		T50	18		T142	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	11		T152	12		T133	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T140	15		T267	1		T91	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T126	9		T154	1		T96	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T154	12		T93	2		T242	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T28	2		T50	5		T229	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T230	2		T155	12		T35	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	1		T16	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T152	5		T137	4		T147	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T133	16		T205	1		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T141	1		T129	5		T251	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T16	7		T17	4		T51	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T20	1		T129	2		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T48	1		T148	1		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T15	1		T19	11		T21	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	4		T128	1		T144	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T141	1		T132	1		T135	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T37	11		T142	9		T133	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	1		T206	4		T176	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T50	19		T140	16		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T14	12		T152	13		T133	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T81	1		T154	13		T267	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T38	1		T47	1		T229	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T130	1		T153	1		T96	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T28	5		T50	6		T206	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T8	4		T128	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T310	10		T242	9		T313	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T18	1		T309	12		T316	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14079	1			T2	20		T3	20		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T147	7		T35	7		T243	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T152	3		T94	1		T96	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T136	18		T231	13		T304	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T129	4		T238	14		T256	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T17	1		T51	15		T136	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T155	14		T136	11		T260	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T148	2		T93	4		T311	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T130	15		T131	16		T253	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	1		T126	12		T154	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T62	1		T237	11		T312	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T37	10		T142	10		T232	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T231	13		T101	4		T208	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T50	16		T148	5		T237	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	9		T152	13		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T154	15		T267	1		T93	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T38	11		T47	1		T229	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T130	10		T153	10		T96	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T28	2		T50	5		T260	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	1		T155	11		T146	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T310	10		T313	3		T265	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T316	11		T317	11		T314	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T146	2		T86	8		T249	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T35	6		T243	7		T311	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T162	1		T157	1		T242	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T8	4		T18	1		T309	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T315	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T318	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T152	5		T146	1		T137	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T133	16		T205	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T147	5		T251	13		T238	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T16	7		T51	11		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T20	1		T141	1		T129	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T17	4		T48	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T129	2		T130	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	4		T144	13		T176	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T15	1		T19	11		T21	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T128	1		T133	9		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T132	2		T206	4		T176	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T37	11		T50	19		T142	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T14	12		T152	13		T133	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T81	1		T140	16		T267	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T47	1		T126	10		T154	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T130	1		T153	1		T154	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T38	1		T28	5		T50	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T128	1		T132	1		T230	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13977	1			T2	20		T3	20		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T342	6		T343	1		T308	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T8	1		T86	3		T208	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T318	19		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T152	3		T146	2		T94	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T136	18		T231	13		T35	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T238	14		T256	9		T270	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T51	15		T136	8		T235	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T129	4		T155	14		T136	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T17	1		T148	2		T311	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T130	15		T237	7		T260	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T13	1		T154	17		T98	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T131	16		T62	1		T253	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T232	13		T126	12		T304	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T231	13		T101	4		T208	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T37	10		T50	16		T142	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T14	9		T152	13		T155	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T267	1		T240	16		T344	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T126	10		T96	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T130	10		T153	10		T154	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T38	11		T28	2		T50	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T155	11		T146	13		T35	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18868

1

T2

20

T3

20

T4

13

auto[1]

auto[0]

4257

1

T8

1

T13

1

T14

9