Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5548	1			T1	20		T2	2		T4	6
testmodes[AdcCtrlTestmodeNormal]	4900	1			T4	7		T7	6		T9	6
testmodes[AdcCtrlTestmodeLowpower]	5022	1			T2	1		T5	15		T10	14
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2781	1			T1	19		T2	1		T4	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1455	1			T4	3		T7	2		T9	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1197	1			T42	1		T57	11		T56	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1492	1			T4	3		T7	2		T9	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1801	1			T4	3		T7	4		T9	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1266	1			T11	1		T12	1		T15	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1169	1			T2	1		T12	1		T42	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1304	1			T11	2		T13	1		T15	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2305	1			T5	14		T10	13		T13	12