Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.67	99.07	96.67	100.00	100.00	98.82	98.33	90.82

Total tests in report: 903

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
59.01	59.01	89.37	89.37	54.47	54.47	83.89	83.89	35.14	35.14	76.16	76.16	67.28	67.28	6.76	6.76	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2765252057
78.29	19.28	98.30	8.93	83.74	29.27	95.97	12.09	70.27	35.14	97.27	21.10	86.81	19.53	15.70	8.93	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1482664675
81.67	3.37	98.82	0.53	92.34	8.60	95.97	0.00	75.68	5.41	98.01	0.74	90.65	3.84	20.19	4.49	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3224760575
84.14	2.47	98.82	0.00	92.38	0.04	95.97	0.00	91.89	16.22	98.08	0.06	90.65	0.00	21.19	1.00	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.1826676510
85.79	1.65	98.82	0.00	93.91	1.52	96.21	0.24	94.59	2.70	98.51	0.43	90.65	0.00	27.85	6.66	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.3617152260
87.19	1.40	98.82	0.00	94.15	0.25	96.21	0.00	94.59	0.00	98.51	0.00	90.82	0.17	37.23	9.38	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.4236998441
88.31	1.12	98.82	0.00	94.15	0.00	96.21	0.00	94.59	0.00	98.51	0.00	90.82	0.00	45.07	7.84	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.2138614634
89.24	0.93	98.88	0.06	94.40	0.25	96.92	0.71	94.59	0.00	98.63	0.12	94.82	4.01	46.44	1.37	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1960067866
89.97	0.72	98.88	0.00	94.40	0.00	96.92	0.00	94.59	0.00	98.63	0.00	94.82	0.00	51.51	5.07	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.1161322381
90.66	0.69	98.88	0.00	94.52	0.12	97.39	0.47	94.59	0.00	98.63	0.00	94.99	0.17	55.60	4.09	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.2613447132
91.26	0.60	98.88	0.00	94.52	0.00	97.39	0.00	97.30	2.70	98.63	0.00	95.16	0.17	56.93	1.32	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.3495822576
91.83	0.58	98.88	0.00	94.52	0.00	97.39	0.00	100.00	2.70	98.63	0.00	95.16	0.00	58.25	1.32	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.2995348898
92.38	0.55	98.88	0.00	94.52	0.00	97.39	0.00	100.00	0.00	98.63	0.00	95.16	0.00	62.09	3.84	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.3091947661
92.87	0.48	98.92	0.03	94.65	0.12	99.76	2.37	100.00	0.00	98.70	0.06	95.83	0.67	62.22	0.12	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.1004929052
93.33	0.46	98.92	0.00	94.65	0.00	99.76	0.00	100.00	0.00	98.70	0.00	95.83	0.00	65.46	3.24	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.315229188
93.75	0.42	98.92	0.00	94.65	0.00	99.76	0.00	100.00	0.00	98.70	0.00	95.83	0.00	68.38	2.92	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.3460649575
94.09	0.35	98.92	0.00	94.65	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.16	0.33	70.48	2.10	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.891681171
94.39	0.29	98.92	0.00	94.65	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.49	0.33	72.20	1.72	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.2883630867
94.64	0.26	98.92	0.00	94.65	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.49	0.00	74.00	1.80	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.3469726867
94.87	0.22	98.92	0.00	95.92	1.28	99.76	0.00	100.00	0.00	98.70	0.00	96.66	0.17	74.10	0.10	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1942147726
95.08	0.22	98.92	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.83	0.17	75.44	1.35	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.347505485
95.28	0.20	98.92	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.83	0.00	76.82	1.37	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.1823502810
95.47	0.19	98.92	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	1.34	76.82	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2922584861
95.63	0.16	98.92	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	0.00	77.91	1.10	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.3398881160
95.77	0.15	98.92	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	0.00	78.96	1.05	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.266911621
95.91	0.14	98.92	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	0.00	79.91	0.95	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.392577885
96.04	0.13	98.92	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	0.00	80.83	0.92	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.3333952887
96.14	0.10	98.92	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	0.00	81.53	0.70	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.3575864402
96.24	0.10	98.92	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	0.00	82.21	0.67	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.1874467817
96.32	0.08	98.92	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	0.00	82.78	0.57	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.2906206975
96.40	0.08	98.92	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	0.00	83.33	0.55	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.3343033879
96.47	0.07	98.92	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	0.00	83.85	0.52	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.4138546331
96.54	0.07	98.92	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.70	0.00	98.16	0.00	84.35	0.50	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.3403298542
96.62	0.07	99.01	0.09	96.09	0.16	100.00	0.24	100.00	0.00	98.70	0.00	98.16	0.00	84.35	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.3546128628
96.68	0.06	99.01	0.00	96.09	0.00	100.00	0.00	100.00	0.00	98.70	0.00	98.16	0.00	84.80	0.45	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.1609248121
96.74	0.06	99.07	0.06	96.34	0.25	100.00	0.00	100.00	0.00	98.82	0.12	98.16	0.00	84.80	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3597069537
96.80	0.06	99.07	0.00	96.34	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.16	0.00	85.23	0.42	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.2689292299
96.86	0.05	99.07	0.00	96.54	0.21	100.00	0.00	100.00	0.00	98.82	0.00	98.16	0.00	85.40	0.17	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.955112270
96.90	0.04	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.16	0.00	85.70	0.30	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.761586268
96.94	0.04	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.16	0.00	86.00	0.30	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.3140941927
96.98	0.04	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.16	0.00	86.27	0.27	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.251181925
97.02	0.04	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.16	0.00	86.52	0.25	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup.3182502939
97.05	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.17	86.60	0.07	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2240512248
97.08	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	86.82	0.22	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.1632443525
97.12	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	87.05	0.22	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.3449212274
97.15	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	87.27	0.22	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.585367961
97.18	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	87.50	0.22	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1006429850
97.21	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	87.70	0.20	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1352497348
97.24	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	87.90	0.20	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.3684406641
97.26	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	88.07	0.17	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.658595716
97.28	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	88.22	0.15	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.397089109
97.30	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	88.37	0.15	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.915506601
97.33	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	88.52	0.15	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.1170414047
97.35	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	88.67	0.15	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3063660758
97.37	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	88.82	0.15	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.3629681787
97.39	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	88.94	0.12	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.184592137
97.40	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.07	0.12	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.2529438506
97.42	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.19	0.12	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_clock_gating.625416299
97.44	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.32	0.12	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.4149236723
97.46	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.44	0.12	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.1809421954
97.47	0.01	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.54	0.10	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.701313633
97.49	0.01	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.64	0.10	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.1799191247
97.50	0.01	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.74	0.10	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.2368915994
97.51	0.01	99.07	0.00	96.58	0.04	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.79	0.05	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.660323850
97.52	0.01	99.07	0.00	96.58	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.87	0.07	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.1861260878
97.54	0.01	99.07	0.00	96.58	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.94	0.07	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.4171074414
97.55	0.01	99.07	0.00	96.58	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.02	0.07	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.990821944
97.56	0.01	99.07	0.00	96.62	0.04	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.04	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.3370696938
97.56	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.09	0.05	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.3382329123
97.57	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.14	0.05	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.2268106498
97.58	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.19	0.05	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.2897692044
97.58	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.24	0.05	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.3158219706
97.59	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.29	0.05	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.3828611558
97.60	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.34	0.05	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt.395337604
97.61	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.39	0.05	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled.2482739318
97.61	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.44	0.05	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.2129423678
97.62	0.01	99.07	0.00	96.62	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.49	0.05	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3015371338
97.63	0.01	99.07	0.00	96.67	0.04	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.49	0.00	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.912428494
97.63	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.52	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.2301095024
97.63	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.54	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.2686513703
97.64	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.57	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.873226574
97.64	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.59	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.2864517115
97.64	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.62	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.1103861717
97.65	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.64	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.1697685543
97.65	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.67	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.3379353030
97.65	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.69	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.3702470740
97.66	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.72	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.4126929470
97.66	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.74	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.790762225
97.66	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.77	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.2532131022
97.67	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.79	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.3610260638
97.67	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.82	0.02	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.408620087

---

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3234105033
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2478139520
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2734608701
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1626293441
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.2102296515
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.206670399
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3593252386
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4130401102
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1302919785
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2755925424
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2859582312
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1186844943
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.2603374599
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.383424974
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3195002921
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.297003182
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3824746694
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.2054393815
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3677260278
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1770614963
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2772026580
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4088913167
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1486717523
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.778686712
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3956522653
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3291823397
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.697003813
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3436396248
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.993810937
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.1028720432
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3990860792
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1659489301
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1611642706
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2261236558
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2384102291
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.1275980436
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.519105910
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3514558754
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2982497130
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3244539967
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.668552374
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2940765315
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.50149289
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1247941832
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4011010951
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2102347838
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.345862456
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.3225793990
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.950295847
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2342700002
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2168297475
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1023078757
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1574151144
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.2069639672
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2066421418
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1350821529
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3669380248
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.343099747
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1342551099
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1037068787
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1482961429
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.4103853032
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3638065813
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2339011043
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.392501437
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1724515072
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2833241639
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2267706043
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.82910786
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3751701144
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3969144350
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4196887591
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2603780229
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.99779522
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.1883796337
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1210813566
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3026331524
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2040598341
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.1415223099
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.3365738052
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.4164170167
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.477496231
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.4003474935
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/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.2320906060
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.553068809
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.3935800557
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/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.3822865051
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/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.3576715007
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/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.2161740008
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.1041911138
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1853703342
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.4166092235
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.318724578
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.2297062765
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/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.496556694
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/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.2473687878
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.590212250
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Total test records in report: 903

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.3674590880			Oct 02 09:11:05 PM UTC 24	Oct 02 09:11:14 PM UTC 24	5998511406 ps
T2	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2765252057			Oct 02 09:11:20 PM UTC 24	Oct 02 09:11:29 PM UTC 24	2597611963 ps
T3	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.3546128628			Oct 02 09:11:30 PM UTC 24	Oct 02 09:11:33 PM UTC 24	420015238 ps
T4	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.1222838517			Oct 02 09:11:16 PM UTC 24	Oct 02 09:11:36 PM UTC 24	3626439811 ps
T21	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.1004929052			Oct 02 09:11:25 PM UTC 24	Oct 02 09:11:44 PM UTC 24	7720906711 ps
T5	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.953684802			Oct 02 09:11:18 PM UTC 24	Oct 02 09:12:01 PM UTC 24	35271537377 ps
T6	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.602226646			Oct 02 09:11:34 PM UTC 24	Oct 02 09:12:01 PM UTC 24	5718954796 ps
T22	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.1497997998			Oct 02 09:12:02 PM UTC 24	Oct 02 09:12:04 PM UTC 24	590208823 ps
T7	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.2734043854			Oct 02 09:11:51 PM UTC 24	Oct 02 09:12:07 PM UTC 24	3146557579 ps
T8	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.2141110647			Oct 02 09:12:03 PM UTC 24	Oct 02 09:12:10 PM UTC 24	5876036984 ps
T47	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.2482434344			Oct 02 09:12:01 PM UTC 24	Oct 02 09:12:20 PM UTC 24	8327212192 ps
T9	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.3432544460			Oct 02 09:12:18 PM UTC 24	Oct 02 09:12:35 PM UTC 24	3220284192 ps
T50	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.2930143749			Oct 02 09:12:37 PM UTC 24	Oct 02 09:12:41 PM UTC 24	492179834 ps
T10	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.1177263127			Oct 02 09:11:54 PM UTC 24	Oct 02 09:12:43 PM UTC 24	32813774963 ps
T51	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.1283374373			Oct 02 09:12:35 PM UTC 24	Oct 02 09:12:52 PM UTC 24	4311744203 ps
T11	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1960067866			Oct 02 09:12:27 PM UTC 24	Oct 02 09:12:55 PM UTC 24	8098380572 ps
T12	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2083414203			Oct 02 09:11:59 PM UTC 24	Oct 02 09:12:57 PM UTC 24	162286272694 ps
T13	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.3045899644			Oct 02 09:11:23 PM UTC 24	Oct 02 09:12:58 PM UTC 24	197407876140 ps
T23	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.858946438			Oct 02 09:12:42 PM UTC 24	Oct 02 09:13:07 PM UTC 24	5881963582 ps
T24	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.4024061639			Oct 02 09:13:04 PM UTC 24	Oct 02 09:13:11 PM UTC 24	3777283603 ps
T14	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.504515777			Oct 02 09:11:38 PM UTC 24	Oct 02 09:13:22 PM UTC 24	167678098751 ps
T15	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1482664675			Oct 02 09:13:07 PM UTC 24	Oct 02 09:13:23 PM UTC 24	18650046772 ps
T25	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.456379014			Oct 02 09:13:18 PM UTC 24	Oct 02 09:13:25 PM UTC 24	4522344452 ps
T26	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.3576996952			Oct 02 09:13:23 PM UTC 24	Oct 02 09:13:27 PM UTC 24	431526413 ps
T27	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.2949386808			Oct 02 09:13:23 PM UTC 24	Oct 02 09:13:32 PM UTC 24	5821454018 ps
T16	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.1908402517			Oct 02 09:11:37 PM UTC 24	Oct 02 09:13:36 PM UTC 24	164545531922 ps
T17	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2240512248			Oct 02 09:11:38 PM UTC 24	Oct 02 09:13:38 PM UTC 24	333947292441 ps
T367	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.245757567			Oct 02 09:12:19 PM UTC 24	Oct 02 09:13:42 PM UTC 24	25226107583 ps
T18	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.2767850928			Oct 02 09:11:14 PM UTC 24	Oct 02 09:13:47 PM UTC 24	172377878980 ps
T97	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.1201000517			Oct 02 09:13:47 PM UTC 24	Oct 02 09:13:54 PM UTC 24	3860155033 ps
T19	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3224760575			Oct 02 09:11:12 PM UTC 24	Oct 02 09:13:58 PM UTC 24	580991626963 ps
T143	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.2167292551			Oct 02 09:13:54 PM UTC 24	Oct 02 09:14:16 PM UTC 24	24644178681 ps
T20	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1492546272			Oct 02 09:14:00 PM UTC 24	Oct 02 09:14:16 PM UTC 24	169767053823 ps
T123	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.1042959750			Oct 02 09:14:18 PM UTC 24	Oct 02 09:14:21 PM UTC 24	390203261 ps
T40	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.4056831561			Oct 02 09:12:15 PM UTC 24	Oct 02 09:14:24 PM UTC 24	203584002494 ps
T86	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.684755921			Oct 02 09:14:17 PM UTC 24	Oct 02 09:14:32 PM UTC 24	4236638313 ps
T124	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.663137083			Oct 02 09:13:05 PM UTC 24	Oct 02 09:14:37 PM UTC 24	33649326501 ps
T125	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.1350170556			Oct 02 09:14:22 PM UTC 24	Oct 02 09:14:37 PM UTC 24	6004137203 ps
T41	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2515220867			Oct 02 09:13:28 PM UTC 24	Oct 02 09:14:54 PM UTC 24	332538906264 ps
T87	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.2613447132			Oct 02 09:11:08 PM UTC 24	Oct 02 09:14:59 PM UTC 24	325368613324 ps
T88	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1697789681			Oct 02 09:12:06 PM UTC 24	Oct 02 09:15:21 PM UTC 24	166941085034 ps
T117	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.2477106497			Oct 02 09:13:26 PM UTC 24	Oct 02 09:15:22 PM UTC 24	165006090581 ps
T141	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.3935800557			Oct 02 09:15:22 PM UTC 24	Oct 02 09:15:26 PM UTC 24	4038757869 ps
T52	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.3455620615			Oct 02 09:13:32 PM UTC 24	Oct 02 09:15:37 PM UTC 24	186576629365 ps
T53	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.658595716			Oct 02 09:11:12 PM UTC 24	Oct 02 09:15:38 PM UTC 24	351956752492 ps
T134	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.216049290			Oct 02 09:15:39 PM UTC 24	Oct 02 09:15:41 PM UTC 24	434699977 ps
T58	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.1589558586			Oct 02 09:12:56 PM UTC 24	Oct 02 09:15:59 PM UTC 24	225388794774 ps
T42	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3038423334			Oct 02 09:15:38 PM UTC 24	Oct 02 09:16:02 PM UTC 24	11734828887 ps
T90	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.2784859675			Oct 02 09:15:42 PM UTC 24	Oct 02 09:16:09 PM UTC 24	5695376123 ps
T91	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.408614893			Oct 02 09:13:38 PM UTC 24	Oct 02 09:16:19 PM UTC 24	164010583225 ps
T92	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.1484604897			Oct 02 09:12:04 PM UTC 24	Oct 02 09:16:35 PM UTC 24	162104055639 ps
T93	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.3617152260			Oct 02 09:11:59 PM UTC 24	Oct 02 09:16:44 PM UTC 24	370045722349 ps
T66	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.2689292299			Oct 02 09:12:58 PM UTC 24	Oct 02 09:16:49 PM UTC 24	363496841628 ps
T94	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.766204518			Oct 02 09:14:37 PM UTC 24	Oct 02 09:16:56 PM UTC 24	170870716128 ps
T95	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.3449212274			Oct 02 09:12:14 PM UTC 24	Oct 02 09:17:08 PM UTC 24	348613731489 ps
T96	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.403297061			Oct 02 09:16:57 PM UTC 24	Oct 02 09:17:09 PM UTC 24	4358431030 ps
T38	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.3379353030			Oct 02 09:13:11 PM UTC 24	Oct 02 09:17:25 PM UTC 24	335035117573 ps
T368	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.553068809			Oct 02 09:15:23 PM UTC 24	Oct 02 09:17:42 PM UTC 24	39911433193 ps
T43	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1525598128			Oct 02 09:17:25 PM UTC 24	Oct 02 09:17:43 PM UTC 24	2812981465 ps
T369	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.3822865051			Oct 02 09:17:43 PM UTC 24	Oct 02 09:17:46 PM UTC 24	552285239 ps
T370	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.532640293			Oct 02 09:17:43 PM UTC 24	Oct 02 09:18:10 PM UTC 24	5640518669 ps
T371	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.446277933			Oct 02 09:17:09 PM UTC 24	Oct 02 09:18:11 PM UTC 24	37719336820 ps
T222	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.2624420028			Oct 02 09:11:14 PM UTC 24	Oct 02 09:18:39 PM UTC 24	162829394816 ps
T372	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.832455378			Oct 02 09:16:03 PM UTC 24	Oct 02 09:19:08 PM UTC 24	165013532615 ps
T118	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.772003840			Oct 02 09:16:33 PM UTC 24	Oct 02 09:19:10 PM UTC 24	169826535227 ps
T119	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.1469874016			Oct 02 09:16:00 PM UTC 24	Oct 02 09:19:17 PM UTC 24	325340641612 ps
T57	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.3370696938			Oct 02 09:13:58 PM UTC 24	Oct 02 09:19:20 PM UTC 24	80950377918 ps
T373	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.2213989838			Oct 02 09:19:20 PM UTC 24	Oct 02 09:19:27 PM UTC 24	4513864443 ps
T243	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2559514444			Oct 02 09:11:43 PM UTC 24	Oct 02 09:19:36 PM UTC 24	205018086622 ps
T126	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.2995348898			Oct 02 09:15:39 PM UTC 24	Oct 02 09:19:44 PM UTC 24	228945059090 ps
T135	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.4090022668			Oct 02 09:14:25 PM UTC 24	Oct 02 09:19:49 PM UTC 24	498859310865 ps
T44	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.451695009			Oct 02 09:19:46 PM UTC 24	Oct 02 09:19:53 PM UTC 24	8700167373 ps
T149	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.745408963			Oct 02 09:12:03 PM UTC 24	Oct 02 09:20:16 PM UTC 24	164535075097 ps
T150	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.1033212151			Oct 02 09:11:45 PM UTC 24	Oct 02 09:19:55 PM UTC 24	178185703226 ps
T151	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3589055712			Oct 02 09:11:12 PM UTC 24	Oct 02 09:19:56 PM UTC 24	321521230294 ps
T152	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.2161740008			Oct 02 09:19:54 PM UTC 24	Oct 02 09:19:56 PM UTC 24	525379448 ps
T153	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.3294942080			Oct 02 09:19:56 PM UTC 24	Oct 02 09:20:11 PM UTC 24	5898385177 ps
T56	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.2033361147			Oct 02 09:11:18 PM UTC 24	Oct 02 09:20:31 PM UTC 24	95688364029 ps
T154	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3206064466			Oct 02 09:14:55 PM UTC 24	Oct 02 09:20:30 PM UTC 24	405196717634 ps
T155	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.3792358666			Oct 02 09:19:27 PM UTC 24	Oct 02 09:20:44 PM UTC 24	23954035624 ps
T120	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.3575864402			Oct 02 09:11:05 PM UTC 24	Oct 02 09:20:55 PM UTC 24	485641262899 ps
T216	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.552356867			Oct 02 09:13:42 PM UTC 24	Oct 02 09:20:58 PM UTC 24	162917447468 ps
T374	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.2600520877			Oct 02 09:11:05 PM UTC 24	Oct 02 09:21:05 PM UTC 24	498447641595 ps
T375	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.1119029398			Oct 02 09:20:48 PM UTC 24	Oct 02 09:21:08 PM UTC 24	4657583162 ps
T121	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.1085307979			Oct 02 09:20:12 PM UTC 24	Oct 02 09:21:10 PM UTC 24	324252574727 ps
T376	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.1639548230			Oct 02 09:21:10 PM UTC 24	Oct 02 09:21:15 PM UTC 24	520967244 ps
T136	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.4166092235			Oct 02 09:17:47 PM UTC 24	Oct 02 09:21:18 PM UTC 24	322422248516 ps
T45	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1090051266			Oct 02 09:21:06 PM UTC 24	Oct 02 09:21:19 PM UTC 24	9780631769 ps
T377	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.365669692			Oct 02 09:21:16 PM UTC 24	Oct 02 09:21:19 PM UTC 24	5698859771 ps
T221	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.2456537254			Oct 02 09:14:33 PM UTC 24	Oct 02 09:21:43 PM UTC 24	166801084192 ps
T215	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.3343033879			Oct 02 09:15:00 PM UTC 24	Oct 02 09:21:46 PM UTC 24	344431756854 ps
T220	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.3356567018			Oct 02 09:13:24 PM UTC 24	Oct 02 09:21:56 PM UTC 24	163701915202 ps
T378	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.4060053510			Oct 02 09:19:57 PM UTC 24	Oct 02 09:22:06 PM UTC 24	161754446002 ps
T137	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1367488001			Oct 02 09:19:08 PM UTC 24	Oct 02 09:22:11 PM UTC 24	606063764222 ps
T379	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.1021318734			Oct 02 09:14:26 PM UTC 24	Oct 02 09:22:22 PM UTC 24	162306979824 ps
T187	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.1785000861			Oct 02 09:21:09 PM UTC 24	Oct 02 09:22:25 PM UTC 24	69676215714 ps
T380	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.3200605345			Oct 02 09:22:22 PM UTC 24	Oct 02 09:22:25 PM UTC 24	3893025412 ps
T122	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.1514691230			Oct 02 09:14:37 PM UTC 24	Oct 02 09:22:26 PM UTC 24	340709515799 ps
T62	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.303766487			Oct 02 09:12:21 PM UTC 24	Oct 02 09:22:27 PM UTC 24	125070410096 ps
T381	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.3112748996			Oct 02 09:20:56 PM UTC 24	Oct 02 09:22:31 PM UTC 24	25631154299 ps
T382	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.496556694			Oct 02 09:22:32 PM UTC 24	Oct 02 09:22:34 PM UTC 24	406096893 ps
T237	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.1521594443			Oct 02 09:19:57 PM UTC 24	Oct 02 09:22:34 PM UTC 24	164831645511 ps
T46	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2340090148			Oct 02 09:22:27 PM UTC 24	Oct 02 09:22:44 PM UTC 24	47770909670 ps
T54	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.2320906060			Oct 02 09:15:28 PM UTC 24	Oct 02 09:22:59 PM UTC 24	106489691482 ps
T383	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1438618089			Oct 02 09:12:57 PM UTC 24	Oct 02 09:23:00 PM UTC 24	605025027657 ps
T384	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.1707771022			Oct 02 09:22:35 PM UTC 24	Oct 02 09:23:00 PM UTC 24	5962941078 ps
T190	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2002582560			Oct 02 09:17:09 PM UTC 24	Oct 02 09:23:08 PM UTC 24	75969187698 ps
T55	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.1826676510			Oct 02 09:11:56 PM UTC 24	Oct 02 09:23:14 PM UTC 24	136971668505 ps
T385	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.590212250			Oct 02 09:22:26 PM UTC 24	Oct 02 09:23:40 PM UTC 24	23145582304 ps
T386	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.3386554333			Oct 02 09:23:58 PM UTC 24	Oct 02 09:24:05 PM UTC 24	5009998797 ps
T188	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.3703502222			Oct 02 09:13:06 PM UTC 24	Oct 02 09:24:07 PM UTC 24	108816545745 ps
T231	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.2829437343			Oct 02 09:16:45 PM UTC 24	Oct 02 09:24:10 PM UTC 24	170695313520 ps
T127	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.2297062765			Oct 02 09:18:55 PM UTC 24	Oct 02 09:24:23 PM UTC 24	356012569621 ps
T387	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.2128333480			Oct 02 09:21:20 PM UTC 24	Oct 02 09:24:27 PM UTC 24	163492605991 ps
T189	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.2143061501			Oct 02 09:19:37 PM UTC 24	Oct 02 09:24:29 PM UTC 24	75244734413 ps
T388	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.1086245826			Oct 02 09:24:27 PM UTC 24	Oct 02 09:24:30 PM UTC 24	317303757 ps
T48	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1335088149			Oct 02 09:24:11 PM UTC 24	Oct 02 09:24:40 PM UTC 24	5084451284 ps
T389	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.785746734			Oct 02 09:24:29 PM UTC 24	Oct 02 09:24:46 PM UTC 24	6153468730 ps
T390	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.1533895567			Oct 02 09:24:06 PM UTC 24	Oct 02 09:25:13 PM UTC 24	38958397350 ps
T128	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.1324660343			Oct 02 09:23:01 PM UTC 24	Oct 02 09:25:13 PM UTC 24	640077980051 ps
T391	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3681557770			Oct 02 09:20:31 PM UTC 24	Oct 02 09:25:29 PM UTC 24	202875822358 ps
T129	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.1533828364			Oct 02 09:21:20 PM UTC 24	Oct 02 09:25:37 PM UTC 24	485384672868 ps
T177	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.315229188			Oct 02 09:22:11 PM UTC 24	Oct 02 09:25:53 PM UTC 24	325998784732 ps
T178	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.2848376048			Oct 02 09:17:39 PM UTC 24	Oct 02 09:26:11 PM UTC 24	114202077302 ps
T179	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.3494494169			Oct 02 09:25:58 PM UTC 24	Oct 02 09:26:14 PM UTC 24	3588950237 ps
T130	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.2949984573			Oct 02 09:11:37 PM UTC 24	Oct 02 09:26:20 PM UTC 24	488649814355 ps
T49	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.4106928657			Oct 02 09:26:15 PM UTC 24	Oct 02 09:26:22 PM UTC 24	1252896039 ps
T180	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.2712692744			Oct 02 09:26:23 PM UTC 24	Oct 02 09:26:27 PM UTC 24	506579599 ps
T181	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1853703342			Oct 02 09:18:40 PM UTC 24	Oct 02 09:26:31 PM UTC 24	167682468943 ps
T182	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.622172984			Oct 02 09:12:53 PM UTC 24	Oct 02 09:26:31 PM UTC 24	339643618907 ps
T183	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.1799191247			Oct 02 09:12:59 PM UTC 24	Oct 02 09:26:34 PM UTC 24	337640885295 ps
T392	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.1826502003			Oct 02 09:25:59 PM UTC 24	Oct 02 09:26:35 PM UTC 24	42042063428 ps
T142	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.840807091			Oct 02 09:12:05 PM UTC 24	Oct 02 09:27:02 PM UTC 24	325838442030 ps
T393	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.3254828758			Oct 02 09:26:37 PM UTC 24	Oct 02 09:27:06 PM UTC 24	5818884214 ps
T394	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.1231230924			Oct 02 09:12:46 PM UTC 24	Oct 02 09:27:09 PM UTC 24	330913826720 ps
T395	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.655479544			Oct 02 09:27:20 PM UTC 24	Oct 02 09:27:23 PM UTC 24	3690941269 ps
T396	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.2283766121			Oct 02 09:22:45 PM UTC 24	Oct 02 09:27:27 PM UTC 24	164265654320 ps
T131	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.891681171			Oct 02 09:21:20 PM UTC 24	Oct 02 09:27:33 PM UTC 24	497828731237 ps
T163	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.728534551			Oct 02 09:27:34 PM UTC 24	Oct 02 09:27:45 PM UTC 24	4230737882 ps
T164	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.187874504			Oct 02 09:27:23 PM UTC 24	Oct 02 09:27:58 PM UTC 24	28966940308 ps
T132	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.4236998441			Oct 02 09:15:18 PM UTC 24	Oct 02 09:27:58 PM UTC 24	526300507462 ps
T165	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.3976990432			Oct 02 09:27:59 PM UTC 24	Oct 02 09:28:01 PM UTC 24	575065958 ps
T166	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.896282966			Oct 02 09:27:59 PM UTC 24	Oct 02 09:28:04 PM UTC 24	5692789866 ps
T133	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.266911621			Oct 02 09:12:48 PM UTC 24	Oct 02 09:28:14 PM UTC 24	497949922192 ps
T167	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.4138027741			Oct 02 09:12:07 PM UTC 24	Oct 02 09:28:16 PM UTC 24	357001280668 ps
T168	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3017320357			Oct 02 09:26:39 PM UTC 24	Oct 02 09:28:26 PM UTC 24	330615607823 ps
T169	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.2138614634			Oct 02 09:22:07 PM UTC 24	Oct 02 09:28:26 PM UTC 24	499790783217 ps
T397	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.318724578			Oct 02 09:18:11 PM UTC 24	Oct 02 09:28:36 PM UTC 24	476571115154 ps
T398	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.2386701619			Oct 02 09:24:41 PM UTC 24	Oct 02 09:28:38 PM UTC 24	168144231183 ps
T219	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1352497348			Oct 02 09:25:30 PM UTC 24	Oct 02 09:28:41 PM UTC 24	532773119323 ps
T399	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.3158339563			Oct 02 09:28:42 PM UTC 24	Oct 02 09:28:48 PM UTC 24	3645745234 ps
T144	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.668527935			Oct 02 09:21:47 PM UTC 24	Oct 02 09:28:57 PM UTC 24	531535671785 ps
T226	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.1041911138			Oct 02 09:19:11 PM UTC 24	Oct 02 09:29:25 PM UTC 24	184994753800 ps
T138	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.3091947661			Oct 02 09:16:50 PM UTC 24	Oct 02 09:29:32 PM UTC 24	551865669704 ps
T400	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.486832939			Oct 02 09:29:42 PM UTC 24	Oct 02 09:29:45 PM UTC 24	285125835 ps
T401	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1948547137			Oct 02 09:21:44 PM UTC 24	Oct 02 09:29:41 PM UTC 24	159913996241 ps
T184	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.2447092797			Oct 02 09:12:44 PM UTC 24	Oct 02 09:29:50 PM UTC 24	326653019811 ps
T89	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.592095164			Oct 02 09:29:26 PM UTC 24	Oct 02 09:29:52 PM UTC 24	21199333029 ps
T402	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.2786279644			Oct 02 09:29:46 PM UTC 24	Oct 02 09:30:15 PM UTC 24	5903777476 ps
T262	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.875829530			Oct 02 09:25:37 PM UTC 24	Oct 02 09:30:15 PM UTC 24	167969313655 ps
T240	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.2887902531			Oct 02 09:11:47 PM UTC 24	Oct 02 09:30:34 PM UTC 24	318598296836 ps
T238	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.866953200			Oct 02 09:26:39 PM UTC 24	Oct 02 09:30:35 PM UTC 24	323948784916 ps
T288	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.2897692044			Oct 02 09:24:31 PM UTC 24	Oct 02 09:30:40 PM UTC 24	165917843226 ps
T245	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.3460649575			Oct 02 09:25:14 PM UTC 24	Oct 02 09:30:42 PM UTC 24	517996048889 ps
T156	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.4237470220			Oct 02 09:11:35 PM UTC 24	Oct 02 09:30:53 PM UTC 24	482050211653 ps
T403	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.2866920874			Oct 02 09:30:54 PM UTC 24	Oct 02 09:31:04 PM UTC 24	3887825258 ps
T404	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1471109481			Oct 02 09:12:11 PM UTC 24	Oct 02 09:31:09 PM UTC 24	397380009515 ps
T361	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.2473687878			Oct 02 09:22:26 PM UTC 24	Oct 02 09:31:12 PM UTC 24	82754872295 ps
T405	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.2338586181			Oct 02 09:28:49 PM UTC 24	Oct 02 09:31:12 PM UTC 24	33796000873 ps
T406	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3602882635			Oct 02 09:23:09 PM UTC 24	Oct 02 09:31:12 PM UTC 24	584766656109 ps
T407	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.3271390631			Oct 02 09:31:13 PM UTC 24	Oct 02 09:31:17 PM UTC 24	291292608 ps
T274	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.397089109			Oct 02 09:26:38 PM UTC 24	Oct 02 09:31:29 PM UTC 24	324080151837 ps
T408	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2995943848			Oct 02 09:16:20 PM UTC 24	Oct 02 09:31:31 PM UTC 24	488666374491 ps
T281	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1744302188			Oct 02 09:31:12 PM UTC 24	Oct 02 09:31:47 PM UTC 24	5554321304 ps
T409	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.3676305399			Oct 02 09:31:05 PM UTC 24	Oct 02 09:31:48 PM UTC 24	43966906495 ps
T251	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.2745436867			Oct 02 09:27:07 PM UTC 24	Oct 02 09:31:49 PM UTC 24	342153333201 ps
T410	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.693961366			Oct 02 09:31:31 PM UTC 24	Oct 02 09:32:01 PM UTC 24	5943475069 ps
T411	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1567246275			Oct 02 09:30:16 PM UTC 24	Oct 02 09:32:27 PM UTC 24	163619052464 ps
T412	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1602459848			Oct 02 09:28:17 PM UTC 24	Oct 02 09:32:31 PM UTC 24	498686913687 ps
T413	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.73617030			Oct 02 09:32:32 PM UTC 24	Oct 02 09:32:38 PM UTC 24	3189705409 ps
T414	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2570983591			Oct 02 09:24:47 PM UTC 24	Oct 02 09:32:41 PM UTC 24	338907863000 ps
T300	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.753326543			Oct 02 09:31:31 PM UTC 24	Oct 02 09:32:45 PM UTC 24	162449364307 ps
T28	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2317856731			Oct 02 09:32:46 PM UTC 24	Oct 02 09:33:04 PM UTC 24	2133591829 ps
T228	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.944570042			Oct 02 09:27:10 PM UTC 24	Oct 02 09:33:23 PM UTC 24	367270168600 ps
T415	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.1839329332			Oct 02 09:33:05 PM UTC 24	Oct 02 09:33:25 PM UTC 24	10113131244 ps
T59	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.408620087			Oct 02 09:20:59 PM UTC 24	Oct 02 09:33:28 PM UTC 24	114521996260 ps
T416	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.2403199251			Oct 02 09:33:24 PM UTC 24	Oct 02 09:33:28 PM UTC 24	526560970 ps
T417	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.1627639555			Oct 02 09:33:26 PM UTC 24	Oct 02 09:33:34 PM UTC 24	5682762142 ps
T227	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.3055334741			Oct 02 09:30:41 PM UTC 24	Oct 02 09:33:40 PM UTC 24	169656754466 ps
T244	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.2115650415			Oct 02 09:32:01 PM UTC 24	Oct 02 09:33:48 PM UTC 24	330820738601 ps
T185	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.347505485			Oct 02 09:19:17 PM UTC 24	Oct 02 09:33:58 PM UTC 24	321895244719 ps
T208	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.3744198751			Oct 02 09:24:08 PM UTC 24	Oct 02 09:34:15 PM UTC 24	116405306892 ps
T418	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1011156294			Oct 02 09:27:03 PM UTC 24	Oct 02 09:34:17 PM UTC 24	609100551286 ps
T419	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.2517130355			Oct 02 09:32:38 PM UTC 24	Oct 02 09:34:20 PM UTC 24	43203887246 ps
T289	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.3536510781			Oct 02 09:33:35 PM UTC 24	Oct 02 09:34:34 PM UTC 24	167217518725 ps
T420	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.3404022485			Oct 02 09:34:21 PM UTC 24	Oct 02 09:34:40 PM UTC 24	4057218015 ps
T421	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.1398449953			Oct 02 09:13:24 PM UTC 24	Oct 02 09:34:44 PM UTC 24	490029407353 ps
T212	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.1632443525			Oct 02 09:32:28 PM UTC 24	Oct 02 09:34:47 PM UTC 24	220251548082 ps
T422	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.2420551666			Oct 02 09:34:35 PM UTC 24	Oct 02 09:34:49 PM UTC 24	30874308864 ps
T423	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.1361762767			Oct 02 09:34:49 PM UTC 24	Oct 02 09:34:51 PM UTC 24	309351881 ps
T217	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1638767092			Oct 02 09:34:45 PM UTC 24	Oct 02 09:34:56 PM UTC 24	3376393584 ps
T213	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.4128671558			Oct 02 09:29:32 PM UTC 24	Oct 02 09:34:58 PM UTC 24	333882930255 ps
T424	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3935345807			Oct 02 09:21:57 PM UTC 24	Oct 02 09:35:10 PM UTC 24	202310395709 ps
T252	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.1161322381			Oct 02 09:30:43 PM UTC 24	Oct 02 09:35:17 PM UTC 24	551164610333 ps
T425	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.825329390			Oct 02 09:34:52 PM UTC 24	Oct 02 09:35:19 PM UTC 24	5864141598 ps
T426	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2039793736			Oct 02 09:31:50 PM UTC 24	Oct 02 09:36:05 PM UTC 24	207135897671 ps
T266	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.2551567732			Oct 02 09:30:35 PM UTC 24	Oct 02 09:36:11 PM UTC 24	361988282074 ps
T269	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.2812484279			Oct 02 09:26:39 PM UTC 24	Oct 02 09:36:12 PM UTC 24	181672317138 ps
T323	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.2268106498			Oct 02 09:22:35 PM UTC 24	Oct 02 09:36:15 PM UTC 24	330781385516 ps
T239	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.1823502810			Oct 02 09:20:32 PM UTC 24	Oct 02 09:36:17 PM UTC 24	514925146180 ps
T256	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.3629681787			Oct 02 09:18:12 PM UTC 24	Oct 02 09:36:18 PM UTC 24	487699719554 ps
T427	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.179094753			Oct 02 09:36:15 PM UTC 24	Oct 02 09:36:19 PM UTC 24	2907679597 ps
T324	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.947738485			Oct 02 09:36:20 PM UTC 24	Oct 02 09:36:39 PM UTC 24	24966370356 ps
T210	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.1154152554			Oct 02 09:27:46 PM UTC 24	Oct 02 09:36:51 PM UTC 24	297503701715 ps
T428	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.1308789395			Oct 02 09:36:52 PM UTC 24	Oct 02 09:36:54 PM UTC 24	386105339 ps
T197	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.2912162481			Oct 02 09:26:12 PM UTC 24	Oct 02 09:36:57 PM UTC 24	130753263887 ps
T429	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.828891464			Oct 02 09:13:36 PM UTC 24	Oct 02 09:36:59 PM UTC 24	600741165661 ps
T430	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.663840952			Oct 02 09:36:55 PM UTC 24	Oct 02 09:37:08 PM UTC 24	5669850202 ps
T232	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.1797606742			Oct 02 09:28:37 PM UTC 24	Oct 02 09:37:11 PM UTC 24	330533636846 ps
T431	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.937180563			Oct 02 09:26:39 PM UTC 24	Oct 02 09:37:15 PM UTC 24	493304333890 ps
T432	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.4275937851			Oct 02 09:20:17 PM UTC 24	Oct 02 09:37:15 PM UTC 24	331913428316 ps
T241	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.2686513703			Oct 02 09:30:16 PM UTC 24	Oct 02 09:37:19 PM UTC 24	502590732469 ps
T194	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.345583125			Oct 02 09:31:10 PM UTC 24	Oct 02 09:37:21 PM UTC 24	98964382407 ps
T195	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.4194976893			Oct 02 09:27:28 PM UTC 24	Oct 02 09:37:42 PM UTC 24	113878354578 ps
T433	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.461140529			Oct 02 09:37:43 PM UTC 24	Oct 02 09:37:49 PM UTC 24	3649670584 ps
T434	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.3234907950			Oct 02 09:34:48 PM UTC 24	Oct 02 09:38:07 PM UTC 24	51477691055 ps
T196	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.2529438506			Oct 02 09:28:58 PM UTC 24	Oct 02 09:38:08 PM UTC 24	100418230832 ps
T139	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.3576715007			Oct 02 09:16:10 PM UTC 24	Oct 02 09:38:25 PM UTC 24	502954308541 ps
T229	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.1300523338			Oct 02 09:20:47 PM UTC 24	Oct 02 09:38:27 PM UTC 24	517453563779 ps
T319	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.4046185232			Oct 02 09:28:02 PM UTC 24	Oct 02 09:38:29 PM UTC 24	491571252727 ps
T435	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.1849316415			Oct 02 09:38:28 PM UTC 24	Oct 02 09:38:31 PM UTC 24	459515984 ps
T362	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2455638194			Oct 02 09:38:09 PM UTC 24	Oct 02 09:38:35 PM UTC 24	3596338461 ps
T436	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.2292011173			Oct 02 09:36:18 PM UTC 24	Oct 02 09:38:35 PM UTC 24	44062464377 ps
T437	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.3808950263			Oct 02 09:33:29 PM UTC 24	Oct 02 09:38:47 PM UTC 24	495734435050 ps
T438	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.342338142			Oct 02 09:37:12 PM UTC 24	Oct 02 09:38:50 PM UTC 24	161286632014 ps
T439	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.1391770598			Oct 02 09:38:30 PM UTC 24	Oct 02 09:38:56 PM UTC 24	5765819550 ps
T327	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.2338305113			Oct 02 09:34:18 PM UTC 24	Oct 02 09:39:12 PM UTC 24	163932036056 ps
T201	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.150295430			Oct 02 09:32:42 PM UTC 24	Oct 02 09:39:30 PM UTC 24	102614360713 ps
T440	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.698866905			Oct 02 09:37:50 PM UTC 24	Oct 02 09:39:46 PM UTC 24	40472711538 ps
T441	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1836205447			Oct 02 09:23:01 PM UTC 24	Oct 02 09:39:51 PM UTC 24	328307215296 ps
T442	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.2928516213			Oct 02 09:39:46 PM UTC 24	Oct 02 09:39:51 PM UTC 24	3298612456 ps
T140	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.488749756			Oct 02 09:28:26 PM UTC 24	Oct 02 09:40:09 PM UTC 24	238333440299 ps
T443	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.732376851			Oct 02 09:39:51 PM UTC 24	Oct 02 09:40:18 PM UTC 24	37816292216 ps
T230	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.392577885			Oct 02 09:31:45 PM UTC 24	Oct 02 09:40:21 PM UTC 24	500878963130 ps
T297	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.86221951			Oct 02 09:40:10 PM UTC 24	Oct 02 09:40:21 PM UTC 24	44755214655 ps
T444	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.598160896			Oct 02 09:40:21 PM UTC 24	Oct 02 09:40:24 PM UTC 24	489470833 ps
T445	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.644584453			Oct 02 09:40:21 PM UTC 24	Oct 02 09:40:30 PM UTC 24	6189578804 ps
T218	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.3469726867			Oct 02 09:34:16 PM UTC 24	Oct 02 09:40:43 PM UTC 24	536587384333 ps
T275	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.469484610			Oct 02 09:33:28 PM UTC 24	Oct 02 09:40:51 PM UTC 24	486267999557 ps
T446	/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.2224092830			Oct 02 09:29:52 PM UTC 24	Oct 02 09:41:19 PM UTC 24	166994310297 ps