Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23321

1

T1

20

T2

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20078

1

T1

20

T2

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3243

1

T11

6

T12

2

T13

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17574

1

T1

20

T2

3

T4

13

auto[1]

5747

1

T11

6

T12

2

T13

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19493

1

T1

20

T2

3

T4

13

auto[1]

3828

1

T12

1

T13

13

T15

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	55	1			T212	26		T213	1		T214	3
values[1]	541	1			T135	1		T136	1		T215	20
values[2]	702	1			T20	3		T93	14		T95	23
values[3]	586	1			T11	6		T93	6		T95	23
values[4]	683	1			T14	13		T15	4		T40	33
values[5]	2851	1			T16	1		T17	17		T19	28
values[6]	787	1			T13	9		T117	8		T53	17
values[7]	631	1			T52	4		T53	14		T150	33
values[8]	757	1			T18	21		T38	13		T119	1
values[9]	1152	1			T12	2		T20	3		T87	5
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	843	1			T20	3		T95	23		T135	1
values[1]	587	1			T93	14		T95	23		T119	1
values[2]	571	1			T11	6		T15	4		T93	6
values[3]	3030	1			T14	13		T16	1		T17	17
values[4]	623	1			T87	8		T44	4		T120	1
values[5]	758	1			T13	9		T117	8		T53	17
values[6]	543	1			T53	14		T216	4		T121	10
values[7]	839	1			T18	21		T52	4		T42	3
values[8]	818	1			T12	2		T20	3		T87	5
values[9]	133	1			T58	1		T217	1		T218	24
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

4023

1

T11

1

T14

12

T15

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T20	2		T128	1		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T95	11		T135	1		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T93	8		T120	1		T122	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T95	11		T119	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	3		T129	1		T219	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	6		T93	1		T132	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1657	1			T16	1		T17	2		T19	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	13		T215	1		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T87	1		T44	3		T128	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T120	1		T221	1		T122	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T91	10		T66	14		T38	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	1		T117	1		T53	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T53	14		T216	4		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T121	1		T45	2		T163	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T52	4		T38	8		T43	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T18	11		T42	3		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T20	2		T66	2		T135	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	1		T87	1		T222	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T58	1		T217	1		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T218	14		T224	15		T225	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T20	1		T169	18		T219	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T95	12		T215	9		T131	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T93	6		T226	14		T157	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T95	12		T133	11		T138	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T15	1		T219	9		T89	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T93	5		T132	14		T219	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T17	15		T40	18		T41	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T215	1		T177	3		T227	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T87	7		T44	1		T131	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T221	12		T177	9		T183	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T91	13		T66	12		T38	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	8		T117	7		T150	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T142	13		T228	11		T229	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T121	9		T230	4		T211	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T38	5		T126	2		T231	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T18	10		T121	7		T232	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T20	1		T66	4		T130	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	1		T87	4		T131	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T223	13		T233	8		T234	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T218	10		T225	12		T235	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T213	1		T214	3		T236	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T212	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T128	1		T169	16		T219	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T135	1		T136	1		T215	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T20	2		T93	8		T122	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T95	11		T119	1		T127	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T120	1		T237	1		T132	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	6		T93	1		T95	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	3		T40	15		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	13		T215	1		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1608	1			T16	1		T17	2		T19	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T120	1		T221	1		T122	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T91	10		T66	14		T38	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	1		T117	1		T53	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T52	4		T53	14		T216	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T150	17		T121	1		T45	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T38	8		T119	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T18	11		T121	1		T46	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T20	2		T58	1		T66	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T12	1		T87	1		T42	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T236	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T212	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T169	18		T219	12		T238	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T215	9		T131	9		T138	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T20	1		T93	6		T226	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T95	12		T133	11		T239	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T132	9		T219	9		T89	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T93	5		T95	12		T132	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T15	1		T40	18		T133	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T215	1		T177	3		T219	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T17	15		T41	8		T87	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T221	12		T183	3		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T91	13		T66	12		T38	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	8		T117	7		T177	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T169	14		T240	9		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T150	16		T121	9		T241	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T38	5		T126	2		T130	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T18	10		T121	7		T232	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T20	1		T66	4		T231	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T12	1		T87	4		T131	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T20	3		T128	1		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T95	13		T135	1		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T93	7		T120	1		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T95	13		T119	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T15	3		T129	1		T219	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	5		T93	6		T132	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T16	1		T17	17		T19	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	1		T215	2		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T87	8		T44	4		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T120	1		T221	13		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T91	14		T66	13		T38	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	9		T117	8		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T53	1		T216	1		T142	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T121	10		T45	2		T163	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T52	1		T38	6		T43	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T18	11		T42	3		T121	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T20	2		T66	5		T135	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	2		T87	5		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T58	1		T217	1		T223	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T218	11		T224	1		T225	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T1	20		T2	3		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T169	15		T219	12		T214	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T95	10		T215	10		T127	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T93	7		T122	2		T167	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T95	10		T167	7		T138	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T15	1		T219	3		T89	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	1		T132	14		T242	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T19	25		T40	14		T243	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	12		T177	10		T227	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T128	7		T169	9		T244	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T122	16		T177	9		T183	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T91	9		T66	13		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T53	16		T150	16		T144	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T53	13		T216	3		T245	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T140	11		T211	9		T246	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T52	3		T38	7		T231	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T18	10		T245	4		T232	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T20	1		T66	1		T183	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T222	8		T118	12		T247	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T233	11		T248	6		T234	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T218	13		T224	14		T249	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T213	1		T214	1		T236	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T212	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T128	1		T169	19		T219	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T135	1		T136	1		T215	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T20	3		T93	7		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T95	13		T119	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T120	1		T237	1		T132	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	5		T93	6		T95	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T15	3		T40	19		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	1		T215	2		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T16	1		T17	17		T19	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T120	1		T221	13		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T91	14		T66	13		T38	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	9		T117	8		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T52	1		T53	1		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T150	17		T121	10		T45	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T38	6		T119	1		T126	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T18	11		T121	8		T46	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T20	2		T58	1		T66	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T12	2		T87	5		T42	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T1	20		T2	3		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T214	2		T236	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T212	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T169	15		T219	12		T250	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T215	10		T167	7		T138	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T93	7		T122	2		T226	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T95	10		T127	1		T239	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T132	8		T167	7		T219	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T11	1		T95	10		T132	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	1		T40	14		T144	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	12		T177	10		T227	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T19	25		T243	8		T154	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T122	16		T183	6		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T91	9		T66	13		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T53	16		T177	9		T138	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T52	3		T53	13		T216	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T150	16		T144	6		T211	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T38	7		T245	15		T228	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T18	10		T232	9		T140	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T20	1		T66	1		T231	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T222	8		T118	12		T245	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

auto[0]

4023

1

T11

1

T14

12

T15

1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23321

1

T1

20

T2

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19922

1

T1

20

T2

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3399

1

T12

2

T13

9

T14

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17254

1

T1

20

T2

3

T4

13

auto[1]

6067

1

T11

6

T14

13

T15

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19493

1

T1

20

T2

3

T4

13

auto[1]

3828

1

T12

1

T13

13

T15

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	4	1			T131	4		-	-		-	-
values[0]	86	1			T38	13		T251	19		T233	29
values[1]	639	1			T119	1		T135	1		T44	4
values[2]	802	1			T12	2		T14	13		T95	23
values[3]	785	1			T15	4		T18	21		T53	14
values[4]	2981	1			T16	1		T17	17		T19	28
values[5]	465	1			T13	9		T87	8		T42	3
values[6]	638	1			T11	6		T93	14		T126	3
values[7]	689	1			T87	5		T118	13		T136	1
values[8]	632	1			T20	3		T53	17		T66	26
values[9]	1024	1			T20	3		T40	33		T66	6
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	947	1			T38	13		T119	1		T135	1
values[1]	732	1			T14	13		T15	4		T58	1
values[2]	791	1			T12	2		T117	8		T53	14
values[3]	2850	1			T16	1		T17	17		T18	21
values[4]	616	1			T13	9		T42	3		T91	23
values[5]	698	1			T11	6		T93	14		T118	13
values[6]	574	1			T87	5		T120	1		T237	1
values[7]	618	1			T20	3		T53	17		T66	26
values[8]	769	1			T40	33		T66	6		T95	23
values[9]	150	1			T20	3		T131	4		T39	5
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

4023

1

T11

1

T14

12

T15

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T38	8		T119	1		T216	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T135	1		T44	3		T45	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T15	3		T58	1		T121	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	13		T95	11		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T93	1		T135	1		T215	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	1		T117	1		T53	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T16	1		T17	2		T19	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T18	11		T52	4		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T42	3		T129	1		T169	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	1		T91	10		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	6		T126	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T93	8		T118	13		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T87	1		T237	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T120	1		T129	1		T252	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T20	2		T43	2		T46	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T53	17		T66	14		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T66	2		T95	11		T122	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	15		T244	13		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T20	2		T131	1		T158	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T39	1		T147	1		T253	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T38	5		T130	10		T132	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T44	1		T177	9		T238	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	1		T121	16		T142	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T95	12		T215	1		T132	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T93	5		T215	9		T131	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	1		T117	7		T252	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T17	15		T41	8		T87	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T18	10		T150	16		T177	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T169	11		T230	3		T254	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	8		T91	13		T221	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T126	2		T183	12		T241	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T93	6		T131	5		T219	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T87	4		T133	2		T238	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T252	19		T255	7		T39	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T20	1		T133	11		T138	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T66	12		T169	14		T241	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T66	4		T95	12		T130	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T40	18		T244	12		T256	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T20	1		T131	3		T158	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T39	4		T253	10		T257	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2