Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23321

1

T1

20

T2

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19771

1

T1

20

T2

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3550

1

T11

6

T12

2

T13

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17691

1

T1

20

T2

3

T4

13

auto[1]

5630

1

T13

9

T16

1

T17

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19493

1

T1

20

T2

3

T4

13

auto[1]

3828

1

T12

1

T13

13

T15

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	46	1			T338	1		T339	25		T340	20
values[0]	98	1			T14	13		T228	15		T280	22
values[1]	682	1			T20	3		T38	13		T215	20
values[2]	428	1			T53	14		T237	1		T131	4
values[3]	770	1			T87	8		T52	4		T95	23
values[4]	768	1			T20	3		T53	17		T95	23
values[5]	2953	1			T13	9		T16	1		T17	17
values[6]	699	1			T93	14		T43	2		T149	1
values[7]	670	1			T11	6		T58	1		T42	3
values[8]	625	1			T15	4		T87	5		T117	8
values[9]	1006	1			T12	2		T18	21		T66	6
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	782	1			T14	13		T20	3		T215	20
values[1]	527	1			T53	14		T122	17		T237	1
values[2]	945	1			T20	3		T87	8		T52	4
values[3]	2978	1			T16	1		T17	17		T19	28
values[4]	643	1			T13	9		T93	14		T66	26
values[5]	598	1			T58	1		T42	3		T43	2
values[6]	676	1			T11	6		T15	4		T117	8
values[7]	610	1			T87	5		T38	9		T222	9
values[8]	841	1			T12	2		T18	21		T119	1
values[9]	129	1			T66	6		T118	13		T127	2
minimum	14592	1			T1	20		T2	3		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

4023

1

T11

1

T14

12

T15

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	13		T20	2		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T215	11		T122	3		T132	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T53	14		T122	17		T183	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T237	1		T48	3		T132	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T87	1		T52	4		T95	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T20	2		T216	4		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T16	1		T17	2		T19	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T40	15		T93	1		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T93	8		T131	1		T163	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	1		T66	14		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T58	1		T42	3		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T43	2		T45	2		T167	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T117	1		T135	1		T231	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	6		T15	3		T91	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T38	3		T222	9		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T87	1		T44	3		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T18	11		T135	1		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	1		T119	1		T150	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T118	13		T330	13		T233	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T66	2		T127	2		T245	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14500	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T341	1		T342	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T20	1		T131	3		T239	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T215	9		T132	9		T133	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T183	3		T219	1		T138	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T132	14		T262	10		T239	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T87	7		T95	12		T130	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T20	1		T132	15		T133	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T17	15		T41	8		T88	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T40	18		T93	5		T126	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T93	6		T131	9		T227	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	8		T66	12		T121	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T139	12		T230	4		T39	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T252	11		T170	5		T286	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T117	7		T231	3		T177	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T15	1		T91	13		T142	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T38	6		T221	12		T169	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T87	4		T44	1		T226	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T18	10		T121	7		T252	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T150	16		T177	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T233	14		T343	13		T291	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T66	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T13	5		T15	3		T38	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T339	12		T340	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T338	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T14	13		T280	11		T344	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T228	14		T345	1		T308	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T20	2		T38	8		T122	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T215	11		T122	3		T132	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T53	14		T131	1		T289	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T237	1		T132	15		T262	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T87	1		T52	4		T95	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T216	4		T48	3		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T53	17		T95	11		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T20	2		T220	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1600	1			T16	1		T17	2		T19	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	1		T40	15		T93	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T93	8		T149	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T43	2		T252	13		T229	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T58	1		T42	3		T231	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	6		T120	1		T45	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T117	1		T38	3		T135	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	3		T87	1		T91	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T18	11		T222	9		T118	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	1		T66	2		T119	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T339	13		T340	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T280	11		T344	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T228	1		T345	10		T308	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T20	1		T38	5		T138	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T215	9		T132	9		T133	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T131	3		T289	5		T256	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T132	14		T262	10		T239	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T87	7		T95	12		T130	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T132	15		T133	2		T169	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T95	12		T215	1		T131	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T20	1		T133	11		T251	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T17	15		T41	8		T88	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	8		T40	18		T93	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T93	6		T240	10		T139	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T252	11		T229	2		T247	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T231	3		T177	3		T230	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T219	9		T244	12		T209	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T117	7		T38	6		T169	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T15	1		T87	4		T91	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T18	10		T121	7		T221	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	1		T66	4		T150	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	1		T20	3		T131	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T215	10		T122	1		T132	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T53	1		T122	1		T183	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T237	1		T48	3		T132	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T87	8		T52	1		T95	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T20	2		T216	1		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T16	1		T17	17		T19	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T40	19		T93	6		T126	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T93	7		T131	10		T163	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	9		T66	13		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T58	1		T42	3		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T43	2		T45	2		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T117	8		T135	1		T231	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T11	5		T15	3		T91	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T38	7		T222	1		T221	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T87	5		T44	4		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T18	11		T135	1		T121	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T12	2		T119	1		T150	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T118	1		T330	1		T233	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T66	5		T127	1		T245	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14583	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T341	1		T342	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	12		T140	11		T146	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T215	10		T122	2		T132	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T53	13		T122	16		T183	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T132	14		T262	8		T239	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T52	3		T95	10		T144	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T20	1		T216	3		T132	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T19	25		T53	16		T95	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T40	14		T138	15		T240	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T93	7		T227	9		T185	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T66	13		T239	10		T214	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T266	12		T246	13		T250	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T167	7		T252	12		T327	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T231	8		T177	10		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	1		T15	1		T91	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T38	2		T222	8		T169	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T144	7		T226	13		T170	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T18	10		T252	19		T214	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T150	16		T177	9		T183	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T118	12		T330	12		T233	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T66	1		T127	1		T245	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T38	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T339	14		T340	11		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T338	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T14	1		T280	12		T344	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T228	2		T345	11		T308	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T20	3		T38	6		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T215	10		T122	1		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T53	1		T131	4		T289	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T237	1		T132	15		T262	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T87	8		T52	1		T95	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T216	1		T48	3		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T53	1		T95	13		T215	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T20	2		T220	1		T133	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T16	1		T17	17		T19	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	9		T40	19		T93	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T93	7		T149	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T43	2		T252	12		T229	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T58	1		T42	3		T231	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	5		T120	1		T45	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T117	8		T38	7		T135	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	3		T87	5		T91	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T18	11		T222	1		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T12	2		T66	5		T119	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T339	11		T340	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T14	12		T280	10		T344	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T228	13		T308	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T38	7		T122	16		T138	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T215	10		T122	2		T132	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T53	13		T146	10		T159	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T132	14		T262	8		T239	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T52	3		T95	10		T183	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T216	3		T132	11		T169	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T53	16		T95	10		T167	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T20	1		T245	14		T228	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T19	25		T243	8		T154	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T40	14		T66	13		T240	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T93	7		T240	10		T266	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T252	12		T327	2		T247	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T231	8		T177	10		T218	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	1		T167	7		T219	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T38	2		T169	15		T70	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	1		T91	9		T128	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T18	10		T222	8		T118	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T66	1		T150	16		T127	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

auto[0]

4023

1

T11

1

T14

12

T15

1