Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23321

1

T1

20

T2

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19738

1

T1

20

T2

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3583

1

T11

6

T13

9

T15

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17567

1

T1

20

T2

3

T4

13

auto[1]

5754

1

T11

6

T14

13

T16

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19493

1

T1

20

T2

3

T4

13

auto[1]

3828

1

T12

1

T13

13

T15

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	240	1			T66	26		T44	4		T131	4
values[0]	18	1			T128	1		T33	6		T301	11
values[1]	804	1			T12	2		T15	4		T95	23
values[2]	677	1			T11	6		T14	13		T52	4
values[3]	582	1			T66	6		T149	1		T216	4
values[4]	515	1			T18	21		T87	8		T42	3
values[5]	566	1			T91	23		T131	6		T133	3
values[6]	728	1			T53	31		T122	3		T127	2
values[7]	688	1			T20	3		T87	5		T58	1
values[8]	682	1			T20	3		T43	2		T126	3
values[9]	3245	1			T13	9		T16	1		T17	17
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	729	1			T12	2		T15	4		T95	23
values[1]	768	1			T11	6		T14	13		T52	4
values[2]	451	1			T18	21		T66	6		T149	1
values[3]	521	1			T87	8		T42	3		T222	9
values[4]	680	1			T91	23		T48	3		T131	6
values[5]	703	1			T20	3		T53	31		T38	13
values[6]	2945	1			T16	1		T17	17		T19	28
values[7]	631	1			T126	3		T150	33		T120	1
values[8]	992	1			T13	9		T40	33		T117	8
values[9]	44	1			T119	1		T131	4		T163	2
minimum	14857	1			T1	20		T2	3		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

4023

1

T11

1

T14

12

T15

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	1		T38	3		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T15	3		T95	11		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	13		T52	4		T93	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T11	6		T95	11		T120	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T18	11		T149	1		T216	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T66	2		T220	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T222	9		T119	1		T128	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T87	1		T42	3		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T91	10		T131	1		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T48	3		T133	1		T251	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T53	14		T38	8		T237	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T20	2		T53	17		T122	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T16	1		T17	2		T19	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T20	2		T58	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T126	1		T142	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T150	17		T120	1		T45	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T40	15		T117	1		T66	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T13	1		T93	8		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T119	1		T256	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T131	1		T163	2		T60	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14606	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T246	1		T158	14		T33	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	1		T38	6		T215	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T15	1		T95	12		T121	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T93	5		T121	7		T183	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T95	12		T142	13		T133	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T18	10		T218	10		T276	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T66	4		T133	11		T244	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T177	3		T169	14		T219	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T87	7		T240	9		T232	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T91	13		T131	5		T239	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T133	2		T251	10		T255	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T38	5		T251	1		T244	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T20	1		T130	23		T132	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T17	15		T41	8		T87	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T20	1		T183	12		T252	29
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T126	2		T142	8		T131	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T150	16		T215	9		T132	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T40	18		T117	7		T66	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	8		T93	6		T262	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T256	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T131	3		T223	13		T260	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	5		T15	3		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T158	11		T33	1		T290	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T66	14		T44	3		T224	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T131	1		T262	9		T60	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T301	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T128	1		T33	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	1		T38	3		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T15	3		T95	11		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	13		T52	4		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	6		T95	11		T120	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T149	1		T216	4		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T66	2		T220	1		T133	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T18	11		T222	9		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T87	1		T42	3		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T91	10		T131	1		T169	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T133	1		T300	1		T275	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T53	14		T251	1		T244	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T53	17		T122	3		T127	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T87	1		T38	8		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T20	2		T58	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T43	2		T126	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T20	2		T120	1		T45	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1654	1			T16	1		T17	2		T19	28
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T13	1		T93	8		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T66	12		T44	1		T320	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T131	3		T262	10		T250	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T33	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	1		T38	6		T221	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	1		T95	12		T121	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T93	5		T121	7		T215	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T95	12		T142	13		T169	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T183	3		T138	12		T276	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T66	4		T133	22		T89	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T18	10		T177	3		T219	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T87	7		T240	9		T289	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T91	13		T131	5		T169	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T133	2		T278	12		T346	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T251	1		T244	12		T39	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T130	10		T132	15		T251	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T87	4		T38	5		T169	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T20	1		T130	13		T183	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T126	2		T142	8		T131	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T20	1		T215	9		T132	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T17	15		T40	18		T41	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T13	8		T93	6		T150	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[values[9]]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	2		T38	7		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T15	3		T95	13		T121	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	1		T52	1		T93	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	5		T95	13		T120	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T18	11		T149	1		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T66	5		T220	1		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T222	1		T119	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T87	8		T42	3		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T91	14		T131	6		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T48	3		T133	3		T251	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T53	1		T38	6		T237	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T20	2		T53	1		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T16	1		T17	17		T19	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T20	3		T58	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T126	3		T142	9		T131	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T150	17		T120	1		T45	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T40	19		T117	8		T66	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T13	9		T93	7		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T119	1		T256	5		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T131	4		T163	2		T60	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14685	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T246	1		T158	12		T33	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T38	2		T226	13		T185	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T15	1		T95	10		T122	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	12		T52	3		T183	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	1		T95	10		T167	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T18	10		T216	3		T144	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T66	1		T245	4		T211	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T222	8		T128	7		T177	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T240	12		T245	15		T276	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T91	9		T239	10		T242	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T251	8		T159	18		T346	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T53	13		T38	7		T244	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T20	1		T53	16		T122	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T19	25		T243	8		T154	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T183	12		T252	21		T232	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T132	14		T140	11		T146	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T150	16		T215	10		T132	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T40	14		T66	13		T118	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T93	7		T262	8		T240	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T229	20		T250	4		T285	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T158	13		T33	1		T290	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T66	13		T44	4		T224	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T131	4		T262	11		T60	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T301	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T128	1		T33	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T12	2		T38	7		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T15	3		T95	13		T121	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	1		T52	1		T93	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	5		T95	13		T120	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T149	1		T216	1		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T66	5		T220	1		T133	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T18	11		T222	1		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T87	8		T42	3		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T91	14		T131	6		T169	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T133	3		T300	1		T275	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T53	1		T251	2		T244	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T53	1		T122	1		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T87	5		T38	6		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T20	2		T58	1		T130	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T43	2		T126	3		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T20	3		T120	1		T45	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T16	1		T17	17		T19	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T13	9		T93	7		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T66	13		T224	2		T320	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T262	8		T250	4		T347	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T301	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T33	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T38	2		T185	6		T229	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	1		T95	10		T122	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	12		T52	3		T219	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	1		T95	10		T167	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T216	3		T183	6		T138	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T66	1		T89	1		T245	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T18	10		T222	8		T128	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T240	12		T245	15		T276	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T91	9		T169	13		T239	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T296	11		T346	12		T348	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T53	13		T244	12		T242	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T53	16		T122	2		T127	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T38	7		T169	15		T266	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T20	1		T183	12		T252	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T132	14		T140	11		T146	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T215	10		T132	8		T138	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T19	25		T40	14		T118	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T93	7		T150	16		T240	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

auto[0]

4023

1

T11

1

T14

12

T15

1