Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23321

1

T1

20

T2

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20446

1

T1

20

T2

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

2875

1

T12

2

T13

9

T14

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17444

1

T1

20

T2

3

T4

13

auto[1]

5877

1

T11

6

T12

2

T13

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19493

1

T1

20

T2

3

T4

13

auto[1]

3828

1

T12

1

T13

13

T15

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	266	1			T20	3		T87	5		T216	4
values[0]	29	1			T131	10		T39	5		T171	12
values[1]	497	1			T87	8		T53	17		T121	10
values[2]	485	1			T15	4		T18	21		T52	4
values[3]	769	1			T14	13		T20	3		T40	33
values[4]	599	1			T91	23		T136	1		T122	3
values[5]	723	1			T11	6		T58	1		T93	6
values[6]	622	1			T12	2		T93	14		T66	26
values[7]	826	1			T38	13		T222	9		T136	1
values[8]	3137	1			T16	1		T17	17		T19	28
values[9]	792	1			T13	9		T66	6		T119	1
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	513	1			T18	21		T87	8		T53	17
values[1]	571	1			T15	4		T40	33		T52	4
values[2]	768	1			T14	13		T20	3		T117	8
values[3]	624	1			T58	1		T91	23		T136	1
values[4]	641	1			T11	6		T93	6		T95	23
values[5]	782	1			T12	2		T93	14		T66	26
values[6]	3130	1			T16	1		T17	17		T19	28
values[7]	644	1			T43	2		T135	1		T121	8
values[8]	755	1			T13	9		T20	3		T53	14
values[9]	192	1			T87	5		T183	10		T228	15
minimum	14701	1			T1	20		T2	3		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

4023

1

T11

1

T14

12

T15

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T18	11		T53	17		T132	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T87	1		T121	1		T237	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T52	4		T44	3		T150	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T15	3		T40	15		T95	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T42	3		T149	1		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	13		T20	2		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T128	1		T129	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T58	1		T91	10		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T11	6		T95	11		T122	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T93	1		T38	3		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T66	14		T222	9		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	1		T93	8		T177	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1725	1			T16	1		T17	2		T19	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T38	8		T163	2		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T43	2		T121	1		T231	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T135	1		T184	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T20	2		T66	2		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	1		T53	14		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T87	1		T228	14		T275	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T183	7		T158	14		T305	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14513	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T131	1		T282	10		T171	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T18	10		T132	9		T228	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T87	7		T121	9		T289	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T44	1		T150	16		T131	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	1		T40	18		T95	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T177	3		T132	14		T169	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T20	1		T117	7		T256	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T142	13		T244	1		T232	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T91	13		T252	19		T157	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T95	12		T219	1		T185	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T93	5		T38	6		T215	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T66	12		T221	12		T130	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	1		T93	6		T177	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T17	15		T41	8		T88	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T38	5		T133	11		T251	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T121	7		T231	3		T183	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T239	6		T211	8		T343	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T20	1		T66	4		T126	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	8		T215	1		T252	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T87	4		T228	1		T314	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T183	3		T158	11		T315	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T13	5		T15	3		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T131	9		T282	5		T171	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T20	2		T87	1		T216	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T215	1		T274	1		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T39	1		T316	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T131	1		T171	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T53	17		T228	13		T185	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T87	1		T121	1		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T18	11		T52	4		T44	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T15	3		T45	2		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T42	3		T149	1		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T14	13		T20	2		T40	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T142	1		T251	9		T244	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T91	10		T136	1		T122	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T11	6		T95	11		T122	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T58	1		T93	1		T119	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T66	14		T120	1		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T93	8		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T222	9		T136	1		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T38	8		T163	2		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1726	1			T16	1		T17	2		T19	28
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T53	14		T135	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T66	2		T126	1		T231	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	1		T119	1		T135	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T20	1		T87	4		T219	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T215	1		T349	13		T350	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T39	4		T316	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T131	9		T171	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T228	11		T185	5		T256	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T87	7		T121	9		T289	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T18	10		T44	1		T150	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T15	1		T133	2		T239	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T177	3		T169	11		T227	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T20	1		T40	18		T117	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T142	13		T251	10		T244	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T91	13		T252	19		T256	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T95	12		T219	1		T185	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T93	5		T215	9		T130	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T66	12		T221	12		T130	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	1		T93	6		T38	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T131	5		T138	22		T240	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T38	5		T133	11		T169	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1125	1			T17	15		T41	8		T88	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T251	1		T239	6		T139	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T66	4		T126	2		T231	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	8		T183	3		T252	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T18	11		T53	1		T132	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T87	8		T121	10		T237	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T52	1		T44	4		T150	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T15	3		T40	19		T95	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T42	3		T149	1		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	1		T20	3		T117	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T128	1		T129	1		T142	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T58	1		T91	14		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	5		T95	13		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T93	6		T38	7		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T66	13		T222	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	2		T93	7		T177	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T16	1		T17	17		T19	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T38	6		T163	2		T133	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T43	2		T121	8		T231	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T135	1		T184	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T20	2		T66	5		T126	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	9		T53	1		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T87	5		T228	2		T275	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T183	4		T158	12		T305	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14596	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T131	10		T282	6		T171	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T18	10		T53	16		T132	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T167	7		T276	13		T258	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T52	3		T150	16		T244	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T15	1		T40	14		T95	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T177	10		T132	14		T167	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	12		T118	12		T229	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T266	4		T218	13		T242	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T91	9		T122	2		T252	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	1		T95	10		T122	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T38	2		T215	10		T128	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T66	13		T222	8		T240	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T93	7		T177	9		T169	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T19	25		T243	8		T154	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T38	7		T232	9		T214	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T231	8		T183	12		T132	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T239	10		T211	9		T224	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T20	1		T66	1		T216	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T53	13		T127	1		T252	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T228	13		T314	8		T254	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T183	6		T158	13		T305	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T214	2		T263	15		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T282	9		T317	21		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T20	2		T87	5		T216	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T215	2		T274	1		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T39	5		T316	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T131	10		T171	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T53	1		T228	12		T185	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T87	8		T121	10		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T18	11		T52	1		T44	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T15	3		T45	2		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T42	3		T149	1		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	1		T20	3		T40	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T142	14		T251	11		T244	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T91	14		T136	1		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	5		T95	13		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T58	1		T93	6		T119	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T66	13		T120	1		T221	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	2		T93	7		T38	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T222	1		T136	1		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T38	6		T163	2		T133	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1470	1			T16	1		T17	17		T19	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T53	1		T135	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T66	5		T126	3		T231	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T13	9		T119	1		T135	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T20	1		T216	3		T219	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T351	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T53	16		T228	12		T185	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T167	7		T276	13		T282	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T18	10		T52	3		T150	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T15	1		T140	11		T250	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T177	10		T167	7		T169	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	12		T40	14		T95	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T251	8		T266	4		T218	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T91	9		T122	2		T252	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	1		T95	10		T122	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T215	10		T330	14		T295	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T66	13		T144	7		T70	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T93	7		T38	2		T128	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T222	8		T144	6		T138	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T38	7		T169	13		T226	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T19	25		T243	8		T154	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T53	13		T239	10		T211	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T66	1		T231	8		T245	33
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T127	1		T183	6		T252	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

auto[0]

4023

1

T11

1

T14

12

T15

1