Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23321

1

T1

20

T2

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20234

1

T1

20

T2

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3087

1

T14

13

T18

21

T117

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17241

1

T1

20

T2

3

T4

13

auto[1]

6080

1

T11

7

T12

3

T15

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19493

1

T1

20

T2

3

T4

13

auto[1]

3828

1

T12

1

T13

13

T15

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	601	1			T11	1		T12	3		T42	1
values[0]	34	1			T132	27		T324	1		T325	6
values[1]	815	1			T18	21		T58	1		T44	4
values[2]	2851	1			T16	1		T17	17		T19	28
values[3]	586	1			T95	23		T136	1		T122	3
values[4]	745	1			T20	3		T117	8		T53	17
values[5]	580	1			T91	23		T38	13		T150	33
values[6]	512	1			T11	6		T14	13		T15	4
values[7]	645	1			T93	6		T119	1		T45	2
values[8]	752	1			T13	9		T20	3		T87	13
values[9]	917	1			T12	2		T95	23		T43	2
minimum	14283	1			T1	20		T2	3		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	660	1			T18	21		T58	1		T44	4
values[1]	2933	1			T16	1		T17	17		T19	28
values[2]	603	1			T95	23		T118	13		T120	1
values[3]	706	1			T20	3		T117	8		T53	17
values[4]	495	1			T91	23		T38	13		T150	33
values[5]	587	1			T11	6		T14	13		T15	4
values[6]	710	1			T13	9		T87	8		T93	6
values[7]	691	1			T20	3		T87	5		T119	1
values[8]	968	1			T12	2		T43	2		T222	9
values[9]	106	1			T95	23		T135	1		T323	1
minimum	14862	1			T1	20		T2	3		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

4023

1

T11

1

T14

12

T15

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T44	3		T130	1		T169	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	11		T58	1		T177	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1664	1			T16	1		T17	2		T19	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T53	14		T136	1		T245	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T118	13		T136	1		T122	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T95	11		T120	1		T219	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T20	2		T53	17		T66	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T117	1		T167	8		T262	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T38	8		T150	17		T120	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T91	10		T215	1		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	6		T15	3		T52	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	13		T42	3		T177	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	1		T87	1		T45	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T93	1		T119	1		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T20	2		T87	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T119	1		T135	1		T122	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	1		T222	9		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T43	2		T121	1		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T95	11		T273	1		T322	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T135	1		T323	1		T60	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14577	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T130	1		T132	9		T324	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T44	1		T130	10		T169	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T18	10		T177	3		T185	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T17	15		T40	18		T41	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T244	1		T256	4		T230	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T226	14		T239	4		T256	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T95	12		T219	9		T299	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T20	1		T66	12		T131	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T117	7		T262	10		T251	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T38	5		T150	16		T133	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T91	13		T215	1		T138	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T15	1		T66	4		T183	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T177	9		T131	5		T252	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	8		T87	7		T240	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T93	5		T219	12		T89	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T20	1		T87	4		T231	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T218	10		T158	11		T286	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	1		T126	2		T121	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T121	7		T221	12		T183	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T95	12		T322	12		T316	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T60	8		T308	12		T321	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	5		T15	3		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T130	13		T132	9		T352	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T11	1		T12	3		T42	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T241	1		T60	1		T348	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T132	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T324	1		T325	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T44	3		T215	11		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T18	11		T58	1		T177	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1643	1			T16	1		T17	2		T19	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T53	14		T136	1		T244	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T136	1		T122	3		T46	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T95	11		T219	4		T245	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T20	2		T53	17		T66	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T117	1		T120	1		T167	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T38	8		T150	17		T120	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T91	10		T215	1		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	6		T15	3		T52	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	13		T42	3		T177	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T45	2		T144	7		T185	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T93	1		T119	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T13	1		T20	2		T87	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T119	1		T135	1		T122	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	1		T95	11		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T43	2		T135	1		T121	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14198	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T121	9		T263	10		T314	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T241	12		T60	8		T348	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T132	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T325	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T44	1		T215	9		T130	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T18	10		T177	3		T130	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1038	1			T17	15		T40	18		T41	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T244	1		T230	4		T334	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T226	14		T239	4		T39	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T95	12		T219	9		T256	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T20	1		T66	12		T131	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T117	7		T262	10		T251	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T38	5		T150	16		T133	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T91	13		T215	1		T138	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T15	1		T66	4		T183	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T177	9		T131	5		T238	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T185	14		T212	12		T239	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T93	5		T89	2		T228	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	8		T20	1		T87	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T219	12		T280	4		T158	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	1		T95	12		T126	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T121	7		T221	12		T183	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T44	4		T130	11		T169	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	11		T58	1		T177	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T16	1		T17	17		T19	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T53	1		T136	1		T245	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T118	1		T136	1		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T95	13		T120	1		T219	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T20	2		T53	1		T66	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T117	8		T167	1		T262	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T38	6		T150	17		T120	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T91	14		T215	2		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	5		T15	3		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	1		T42	3		T177	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	9		T87	8		T45	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T93	6		T119	1		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T20	3		T87	5		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T119	1		T135	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T12	2		T222	1		T126	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T43	2		T121	8		T221	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T95	13		T273	1		T322	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T135	1		T323	1		T60	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14673	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T130	14		T132	10		T324	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T169	9		T144	7		T252	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T18	10		T177	10		T185	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T19	25		T40	14		T93	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T53	13		T245	15		T326	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T118	12		T122	2		T226	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T95	10		T219	3		T327	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T20	1		T53	16		T66	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T167	7		T262	8		T330	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T38	7		T150	16		T169	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T91	9		T138	15		T245	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	1		T15	1		T52	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	12		T177	9		T252	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T144	6		T240	12		T185	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T219	12		T89	1		T228	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T231	8		T244	12		T242	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T122	16		T266	4		T218	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T222	8		T245	4		T228	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T183	6		T167	7		T251	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T95	10		T322	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T308	3		T328	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T215	10		T132	11		T138	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T132	8		T265	7		T224	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T11	1		T12	3		T42	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T241	13		T60	9		T348	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T132	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T324	1		T325	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T44	4		T215	10		T130	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T18	11		T58	1		T177	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T16	1		T17	17		T19	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T53	1		T136	1		T244	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T136	1		T122	1		T46	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T95	13		T219	10		T245	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T20	2		T53	1		T66	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T117	8		T120	1		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T38	6		T150	17		T120	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T91	14		T215	2		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	5		T15	3		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	1		T42	3		T177	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T45	2		T144	1		T185	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T93	6		T119	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	9		T20	3		T87	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T119	1		T135	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T12	2		T95	13		T126	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T43	2		T135	1		T121	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14283	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T222	8		T245	4		T263	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T348	6		T172	16		T308	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T132	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T215	10		T144	7		T138	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T18	10		T177	10		T132	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T19	25		T40	14		T93	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T53	13		T326	1		T174	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T122	2		T226	13		T239	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T95	10		T219	3		T245	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T20	1		T53	16		T66	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T167	7		T262	8		T330	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T38	7		T150	16		T169	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T91	9		T138	15		T245	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	1		T15	1		T52	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T14	12		T177	9		T266	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T144	6		T185	18		T212	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T89	1		T228	13		T252	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T231	8		T240	12		T244	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T122	16		T219	12		T266	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T95	10		T228	12		T297	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T183	6		T167	7		T251	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

auto[0]

4023

1

T11

1

T14

12

T15

1