Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23321

1

T1

20

T2

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20060

1

T1

20

T2

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3261

1

T11

6

T12

2

T13

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17555

1

T1

20

T2

3

T4

13

auto[1]

5766

1

T11

6

T12

2

T13

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19493

1

T1

20

T2

3

T4

13

auto[1]

3828

1

T12

1

T13

13

T15

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	246	1			T58	1		T120	1		T49	1
values[0]	29	1			T212	26		T214	3		-	-
values[1]	502	1			T135	1		T136	1		T215	20
values[2]	778	1			T20	3		T93	14		T95	46
values[3]	578	1			T11	6		T93	6		T136	1
values[4]	727	1			T14	13		T15	4		T40	33
values[5]	2881	1			T16	1		T17	17		T19	28
values[6]	676	1			T13	9		T117	8		T53	17
values[7]	664	1			T52	4		T53	14		T150	33
values[8]	746	1			T18	21		T38	13		T119	1
values[9]	918	1			T12	2		T20	3		T87	5
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	596	1			T20	3		T95	23		T135	1
values[1]	743	1			T93	14		T95	23		T119	1
values[2]	499	1			T11	6		T15	4		T93	6
values[3]	3072	1			T14	13		T16	1		T17	17
values[4]	632	1			T91	23		T44	4		T120	1
values[5]	723	1			T13	9		T117	8		T53	17
values[6]	543	1			T53	14		T150	33		T216	4
values[7]	822	1			T18	21		T52	4		T38	13
values[8]	826	1			T12	2		T20	3		T87	5
values[9]	151	1			T58	1		T218	24		T224	15
minimum	14714	1			T1	20		T2	3		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

4023

1

T11

1

T14

12

T15

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T20	2		T129	1		T169	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T95	11		T135	1		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T93	8		T120	1		T122	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T95	11		T119	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	3		T237	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	6		T93	1		T132	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1658	1			T16	1		T17	2		T19	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	13		T215	1		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T91	10		T44	3		T128	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T120	1		T221	1		T122	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T66	14		T38	3		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	1		T117	1		T53	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T53	14		T216	4		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T150	17		T121	1		T45	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T52	4		T38	8		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T18	11		T121	1		T46	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T20	2		T66	2		T43	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	1		T87	1		T42	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T58	1		T233	12		T248	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T218	14		T224	15		T334	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14530	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T215	11		T331	1		T263	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T20	1		T169	18		T238	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T95	12		T131	9		T138	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T93	6		T226	14		T157	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T95	12		T133	11		T239	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T15	1		T219	9		T89	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T93	5		T132	14		T256	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T17	15		T40	18		T41	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T215	1		T177	3		T219	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T91	13		T44	1		T131	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T221	12		T177	9		T183	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T66	12		T38	6		T142	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	8		T117	7		T185	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T142	13		T228	11		T229	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T150	16		T121	9		T230	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T38	5		T126	2		T231	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T18	10		T121	7		T232	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T20	1		T66	4		T130	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	1		T87	4		T131	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T233	8		T234	6		T290	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T218	10		T334	12		T353	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T13	5		T15	3		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T215	9		T263	10		T271	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T58	1		T120	1		T49	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T218	14		T39	6		T317	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T214	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T212	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T128	1		T169	16		T219	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T135	1		T136	1		T215	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T20	2		T93	8		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T95	22		T119	1		T127	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T237	1		T129	1		T167	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T11	6		T93	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T15	3		T40	15		T132	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	13		T215	1		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1631	1			T16	1		T17	2		T19	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T120	1		T221	1		T122	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T91	10		T66	14		T38	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	1		T117	1		T53	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T52	4		T53	14		T216	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T150	17		T121	1		T45	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T38	8		T119	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T18	11		T121	1		T46	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T20	2		T66	2		T43	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T12	1		T87	1		T42	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T289	5		T241	12		T223	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T218	10		T39	5		T159	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T212	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T169	18		T219	12		T238	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T215	9		T131	9		T138	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T20	1		T93	6		T226	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T95	24		T133	11		T252	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T219	9		T89	2		T241	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T93	5		T132	14		T256	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T15	1		T40	18		T132	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T215	1		T177	3		T219	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T17	15		T41	8		T87	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T221	12		T183	3		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T91	13		T66	12		T38	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	8		T117	7		T177	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T169	14		T240	9		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T150	16		T121	9		T230	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T38	5		T126	2		T130	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T18	10		T121	7		T232	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T20	1		T66	4		T231	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	1		T87	4		T131	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T20	3		T129	1		T169	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T95	13		T135	1		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T93	7		T120	1		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T95	13		T119	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T15	3		T237	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	5		T93	6		T132	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T16	1		T17	17		T19	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	1		T215	2		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T91	14		T44	4		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T120	1		T221	13		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T66	13		T38	7		T142	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	9		T117	8		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T53	1		T216	1		T142	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T150	17		T121	10		T45	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T52	1		T38	6		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T18	11		T121	8		T46	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T20	2		T66	5		T43	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	2		T87	5		T42	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T58	1		T233	9		T248	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T218	11		T224	1		T334	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14610	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T215	10		T331	1		T263	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T169	15		T146	2		T271	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T95	10		T127	1		T138	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T93	7		T122	2		T167	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T95	10		T167	7		T239	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T15	1		T219	3		T89	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	1		T132	14		T148	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T19	25		T40	14		T243	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	12		T177	10		T227	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T91	9		T128	7		T169	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T122	16		T177	9		T183	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T66	13		T38	2		T169	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T53	16		T144	6		T185	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T53	13		T216	3		T245	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T150	16		T140	11		T211	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T52	3		T38	7		T231	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T18	10		T245	4		T232	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T20	1		T66	1		T183	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T222	8		T118	12		T262	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T233	11		T248	6		T234	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T218	13		T224	14		T353	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T219	12		T214	2		T250	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T215	10		T263	8		T271	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T58	1		T120	1		T49	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T218	11		T39	6		T317	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T214	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T212	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T128	1		T169	19		T219	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T135	1		T136	1		T215	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T20	3		T93	7		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T95	26		T119	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T237	1		T129	1		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	5		T93	6		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	3		T40	19		T132	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	1		T215	2		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T16	1		T17	17		T19	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T120	1		T221	13		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T91	14		T66	13		T38	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	9		T117	8		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T52	1		T53	1		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T150	17		T121	10		T45	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T38	6		T119	1		T126	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T18	11		T121	8		T46	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T20	2		T66	5		T43	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	2		T87	5		T42	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T313	11		T234	8		T354	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T218	13		T39	5		T317	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T214	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T212	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T169	15		T219	12		T250	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T215	10		T138	9		T159	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T93	7		T122	2		T226	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T95	20		T127	1		T167	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T167	7		T219	3		T89	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T11	1		T132	14		T148	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T15	1		T40	14		T132	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	12		T177	10		T227	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T19	25		T243	8		T154	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T122	16		T183	6		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T91	9		T66	13		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T53	16		T177	9		T138	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T52	3		T53	13		T216	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T150	16		T144	6		T211	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T38	7		T245	15		T228	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	10		T232	9		T140	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T20	1		T66	1		T231	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T222	8		T118	12		T262	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

auto[0]

4023

1

T11

1

T14

12

T15

1