Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23321

1

T1

20

T2

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19921

1

T1

20

T2

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3400

1

T12

2

T13

9

T14

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17254

1

T1

20

T2

3

T4

13

auto[1]

6067

1

T11

6

T14

13

T15

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19493

1

T1

20

T2

3

T4

13

auto[1]

3828

1

T12

1

T13

13

T15

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	218	1			T95	23		T122	17		T183	10
values[0]	102	1			T38	13		T251	19		T233	29
values[1]	678	1			T119	1		T135	1		T44	4
values[2]	759	1			T14	13		T15	4		T95	23
values[3]	808	1			T12	2		T18	21		T53	14
values[4]	2866	1			T16	1		T17	17		T19	28
values[5]	574	1			T13	9		T87	8		T42	3
values[6]	606	1			T11	6		T93	14		T126	3
values[7]	680	1			T87	5		T118	13		T120	1
values[8]	582	1			T20	3		T53	17		T43	2
values[9]	872	1			T20	3		T40	33		T66	32
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	728	1			T119	1		T135	1		T44	4
values[1]	734	1			T14	13		T15	4		T58	1
values[2]	839	1			T12	2		T18	21		T117	8
values[3]	2738	1			T16	1		T17	17		T19	28
values[4]	686	1			T13	9		T42	3		T91	23
values[5]	693	1			T11	6		T93	14		T118	13
values[6]	535	1			T87	5		T120	1		T237	1
values[7]	615	1			T20	3		T53	17		T66	26
values[8]	841	1			T20	3		T40	33		T66	6
values[9]	81	1			T131	4		T147	1		T158	23
minimum	14831	1			T1	20		T2	3		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

4023

1

T11

1

T14

12

T15

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T119	1		T216	4		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T135	1		T44	3		T45	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	3		T58	1		T121	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	13		T95	11		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T93	1		T38	3		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	1		T18	11		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1512	1			T16	1		T17	2		T19	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T52	4		T135	1		T150	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T42	3		T129	1		T169	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	1		T91	10		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	6		T126	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T93	8		T118	13		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T87	1		T237	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T120	1		T129	1		T244	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T20	2		T43	2		T46	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T53	17		T66	14		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T20	2		T66	2		T95	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T40	15		T244	13		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T131	1		T158	12		T267	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T147	1		T31	1		T257	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14558	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T177	10		T159	15		T295	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T130	10		T132	15		T169	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T44	1		T238	11		T185	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T121	16		T142	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T95	12		T215	1		T132	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T93	5		T38	6		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T18	10		T117	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T17	15		T41	8		T87	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T150	16		T177	3		T142	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T169	11		T230	3		T263	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	8		T91	13		T221	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T126	2		T183	12		T241	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T93	6		T131	5		T219	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T87	4		T133	2		T238	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T244	1		T252	19		T255	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T20	1		T133	11		T138	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T66	12		T169	14		T256	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T20	1		T66	4		T95	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	18		T244	12		T256	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T131	3		T158	11		T267	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T257	2		T309	13		T355	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	5		T15	3		T38	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T177	9		T159	16		T295	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T95	11		T122	17		T183	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T266	13		T256	1		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T38	8		T251	9		T306	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T233	15		T159	15		T356	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T119	1		T216	4		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T135	1		T44	3		T45	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	3		T121	2		T169	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	13		T95	11		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T58	1		T93	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	1		T18	11		T53	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1557	1			T16	1		T17	2		T19	28
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T117	1		T52	4		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T87	1		T42	3		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	1		T91	10		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	6		T126	1		T183	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T93	8		T149	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T87	1		T136	1		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T118	13		T120	1		T127	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T20	2		T43	2		T46	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T53	17		T119	1		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T20	2		T66	2		T122	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T40	15		T66	14		T169	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T95	12		T183	3		T131	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T256	6		T257	2		T309	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T38	5		T251	10		T306	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T233	14		T159	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T130	10		T132	15		T185	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T44	1		T177	9		T238	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T15	1		T121	16		T169	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T95	12		T215	1		T132	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T93	5		T215	9		T142	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	1		T18	10		T252	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T17	15		T41	8		T88	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T117	7		T150	16		T142	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T87	7		T230	3		T309	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	8		T91	13		T221	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T126	2		T183	12		T169	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T93	6		T138	12		T229	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T87	4		T133	2		T238	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T131	5		T219	12		T244	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T20	1		T130	13		T133	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T230	5		T334	9		T172	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T20	1		T66	4		T132	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T40	18		T66	12		T169	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T119	1		T216	1		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T135	1		T44	4		T45	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	3		T58	1		T121	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T14	1		T95	13		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T93	6		T38	7		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	2		T18	11		T117	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T16	1		T17	17		T19	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T52	1		T135	1		T150	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T42	3		T129	1		T169	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	9		T91	14		T221	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	5		T126	3		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T93	7		T118	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T87	5		T237	1		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T120	1		T129	1		T244	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T20	2		T43	2		T46	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T53	1		T66	13		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T20	3		T66	5		T95	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T40	19		T244	13		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T131	4		T158	12		T267	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T147	1		T31	1		T257	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14640	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T177	10		T159	17		T295	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T216	3		T132	11		T169	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T185	6		T229	20		T209	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T15	1		T245	4		T227	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	12		T95	10		T132	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T38	2		T215	10		T128	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T18	10		T53	13		T222	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T19	25		T243	8		T154	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T52	3		T150	16		T177	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T169	9		T263	15		T254	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T91	9		T231	8		T226	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T11	1		T183	12		T336	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T93	7		T118	12		T127	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T228	13		T246	13		T264	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T252	19		T265	7		T39	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T20	1		T167	7		T138	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T53	16		T66	13		T167	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T66	1		T95	10		T122	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T40	14		T244	12		T266	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T158	11		T267	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T257	5		T355	1		T301	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T38	7		T251	8		T242	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T177	9		T159	14		T295	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T95	13		T122	1		T183	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T266	1		T256	7		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T38	6		T251	11		T306	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T233	15		T159	17		T356	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T119	1		T216	1		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T135	1		T44	4		T45	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T15	3		T121	18		T169	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T14	1		T95	13		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T58	1		T93	6		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	2		T18	11		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T16	1		T17	17		T19	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T117	8		T52	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T87	8		T42	3		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	9		T91	14		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	5		T126	3		T183	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T93	7		T149	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T87	5		T136	1		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T118	1		T120	1		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T20	2		T43	2		T46	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T53	1		T119	1		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T20	3		T66	5		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T40	19		T66	13		T169	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T95	10		T122	16		T183	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T266	12		T257	5		T268	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T38	7		T251	8		T306	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T233	14		T159	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T216	3		T132	11		T185	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T177	9		T185	6		T209	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	1		T169	15		T245	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	12		T95	10		T132	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T215	10		T128	7		T240	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T18	10		T53	13		T222	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T19	25		T38	2		T243	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T52	3		T150	16		T219	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T254	9		T270	4		T261	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T91	9		T231	8		T177	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	1		T183	12		T169	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T93	7		T138	15		T245	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T228	13		T246	13		T264	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T118	12		T127	1		T219	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T20	1		T167	7		T138	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T53	16		T167	7		T224	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T66	1		T122	2		T132	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T40	14		T66	13		T169	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

auto[0]

4023

1

T11

1

T14

12

T15

1