Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
* [maximum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 1 1 T131 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 35 1 T38 8 T251 9 T258 12
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 15 1 T233 15 - - - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 193 1 T119 1 T216 4 T129 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 166 1 T135 1 T44 3 T45 2
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 214 1 T121 1 T163 2 T169 16
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 242 1 T12 1 T14 13 T95 11
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 223 1 T15 3 T58 1 T93 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 200 1 T18 11 T53 14 T222 9
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 1575 1 T16 1 T17 2 T19 28
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 207 1 T117 1 T52 4 T135 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 97 1 T87 1 T42 3 T129 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 161 1 T13 1 T91 10 T120 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 174 1 T11 6 T126 1 T149 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 207 1 T93 8 T136 1 T226 14
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 127 1 T87 1 T136 1 T237 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 267 1 T118 13 T127 2 T129 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 183 1 T20 2 T43 2 T122 3
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 181 1 T53 17 T66 14 T119 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 297 1 T20 2 T66 2 T95 11
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 237 1 T40 15 T169 14 T156 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14491 1 T1 20 T2 3 T4 13
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 3 1 T131 3 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 22 1 T38 5 T251 10 T258 3
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 14 1 T233 14 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 153 1 T130 10 T132 15 T185 14
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 127 1 T44 1 T177 9 T238 11
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 148 1 T121 7 T169 18 T211 8
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 198 1 T12 1 T95 12 T132 9
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 203 1 T15 1 T93 5 T121 9
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 159 1 T18 10 T215 1 T259 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 1027 1 T17 15 T41 8 T88 5
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 172 1 T117 7 T150 16 T221 12
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 67 1 T87 7 T254 6 T260 2
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 140 1 T13 8 T91 13 T231 3
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 105 1 T126 2 T183 12 T169 11
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 152 1 T93 6 T226 14 T138 12
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 126 1 T87 4 T133 13 T238 2
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 169 1 T131 5 T219 12 T244 1
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 125 1 T20 1 T130 13 T89 2
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 143 1 T66 12 T230 5 T218 10
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 248 1 T20 1 T66 4 T95 12
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 242 1 T40 18 T169 14 T244 12
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 85 1 T13 5 T15 3 T38 2


Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 7 41 85.42 7


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [maximum] * -- -- 2
[auto[1]] [maximum] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 257 1 T38 6 T119 1 T216 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 260 1 T135 1 T44 4 T45 2
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 206 1 T15 3 T58 1 T121 18
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 207 1 T14 1 T95 13 T120 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 231 1 T93 6 T135 1 T215 10
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 192 1 T12 2 T117 8 T53 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1329 1 T16 1 T17 17 T19 3
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T18 11 T52 1 T135 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 115 1 T42 3 T129 1 T169 12
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 216 1 T13 9 T91 14 T221 13
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 120 1 T11 5 T126 3 T149 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 224 1 T93 7 T118 1 T136 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 178 1 T87 5 T237 1 T133 3
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 123 1 T120 1 T129 1 T252 20
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 159 1 T20 2 T43 2 T46 2
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T53 1 T66 13 T119 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 248 1 T66 5 T95 13 T122 2
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 221 1 T40 19 T244 13 T217 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 39 1 T20 3 T131 4 T158 12
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 57 1 T39 5 T147 1 T253 11
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14576 1 T1 20 T2 3 T4 13
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 226 1 T38 7 T216 3 T132 11
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 204 1 T177 9 T185 6 T229 20
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 158 1 T15 1 T169 15 T245 4
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 161 1 T14 12 T95 10 T132 8
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 189 1 T215 10 T128 7 T144 7
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 179 1 T53 13 T222 8 T252 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1208 1 T19 25 T38 2 T243 8
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 151 1 T18 10 T52 3 T150 16
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 112 1 T169 9 T254 9 T261 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 173 1 T91 9 T231 8 T262 8
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 98 1 T11 1 T183 12 T263 15
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 256 1 T93 7 T118 12 T127 1
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 149 1 T228 13 T246 13 T264 7
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 124 1 T252 19 T265 7 T39 5
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 143 1 T20 1 T167 7 T138 6
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 138 1 T53 16 T66 13 T167 7
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 160 1 T66 1 T95 10 T122 18
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 140 1 T40 14 T244 12 T266 12
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 21 1 T158 11 T267 10 - -
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 33 1 T253 9 T257 5 T268 6


Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[1]] [maximum] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [maximum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 4 1 T131 4 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 29 1 T38 6 T251 11 T258 4
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 15 1 T233 15 - - - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 187 1 T119 1 T216 1 T129 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 163 1 T135 1 T44 4 T45 2
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 182 1 T121 8 T163 2 T169 19
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 240 1 T12 2 T14 1 T95 13
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 250 1 T15 3 T58 1 T93 6
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 192 1 T18 11 T53 1 T222 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 1364 1 T16 1 T17 17 T19 3
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 206 1 T117 8 T52 1 T135 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 93 1 T87 8 T42 3 T129 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 166 1 T13 9 T91 14 T120 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 139 1 T11 5 T126 3 T149 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 184 1 T93 7 T136 1 T226 15
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 153 1 T87 5 T136 1 T237 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 205 1 T118 1 T127 1 T129 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 162 1 T20 2 T43 2 T122 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 171 1 T53 1 T66 13 T119 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 319 1 T20 3 T66 5 T95 13
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 298 1 T40 19 T169 15 T156 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14576 1 T1 20 T2 3 T4 13
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 28 1 T38 7 T251 8 T258 11
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 14 1 T233 14 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 159 1 T216 3 T132 11 T185 18
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 130 1 T177 9 T185 6 T209 9
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 180 1 T169 15 T245 4 T269 17
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 200 1 T14 12 T95 10 T132 8
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 176 1 T15 1 T215 10 T128 7
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 167 1 T18 10 T53 13 T222 8
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 1238 1 T19 25 T38 2 T243 8
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 173 1 T52 3 T150 16 T219 3
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 71 1 T254 9 T270 4 T261 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 135 1 T91 9 T231 8 T177 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 140 1 T11 1 T183 12 T169 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T93 7 T226 13 T138 15
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 100 1 T228 13 T264 7 T271 14
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 231 1 T118 12 T127 1 T219 12
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 146 1 T20 1 T122 2 T167 7
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T53 16 T66 13 T167 7
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 226 1 T66 1 T95 10 T122 16
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 181 1 T40 14 T169 13 T244 12


Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cp   clk_gate_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 19298 1 T1 20 T2 3 T4 13
auto[1] auto[0] 4023 1 T11 1 T14 12 T15 1